/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* TypeDef Declarations                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_TYPEDEF_CLASSES
#undef GET_TYPEDEF_CLASSES


namespace mlir {
class AsmParser;
class AsmPrinter;
} // namespace mlir
namespace mlir::amdgpu {

/// Pair of base addresses that move data between LDS and global storage.
/// This type is opaque and it is used to represent a struct of two addresses.
/// One address is in LDS while the other is in global memory.
/// 
/// The value defined by this operation is only intended to be used by
/// amdgpu.tdm_make_descriptor.
class TDMBaseType;
/// Pair of base addresses that move data between LDS and global storage.
/// This type is opaque and it is used to represent a struct of two addresses.
/// One address is in LDS while the other is in global memory.
/// 
/// This operation is similar to amdgpu.tdm_make_base but intended to be
/// used in gather mode.
/// 
/// The value defined by this operation is only intended to be used by
/// amdgpu.tdm_make_gather_descriptor.
class TDMGatherBaseType;
/// Descriptors used in tensor store/load operations.
/// This type is opaque and corresponds to the two or four descriptor groups
/// used in tensor_load_to_lds or tensor_store_from_lds.
class TDMDescriptorType;
/// State of an in-LDS barrier.
/// Type that encodes the state of an in-LDS barrier as used by the atomic barrier
/// instructions introduced on gfx1250.
/// 
/// It consists of a 29-bit count of the number of pending arrivals at the barrier (the
/// *pending count*) in bits [28:0], a 3-bit *phase* in bits [31:29], and the 32-bit count
/// to re-initialize the pending count to on phase change (the *init count*) in bits [63:32].
/// 
/// When an instruction (either one of the explicit arrival primitives or tensor data
/// movement) *arrives* at such a barrier, the pending count is decremented. If this
/// decrement would cause the pending count to underflow, the count is instead reset
/// to the init count and the phase is decremented (wrapping back to 0). When the
/// phase is decremented, sleeping waves are woken up so they can check the barrier.
/// 
/// The barrier state resides in LDS, but an old barrier state can be returned from atomic
/// arrival instructions or though atomic loads.
/// 
/// This feature is not available prior to gfx1250.
class DsBarrierStateType;
namespace detail {

struct TDMBaseTypeStorage;

} // namespace detail
class TDMBaseType : public ::mlir::Type::TypeBase<TDMBaseType, ::mlir::Type, detail::TDMBaseTypeStorage> {
public:
  using Base::Base;
  static constexpr ::llvm::StringLiteral name = "amdgpu.tdm_base";
  static constexpr ::llvm::StringLiteral dialectName = "amdgpu";
  static TDMBaseType get(::mlir::MLIRContext *context, Type elementType);
  static TDMBaseType get(Type elementType);
  static constexpr ::llvm::StringLiteral getMnemonic() {
    return {"tdm_base"};
  }

  static ::mlir::Type parse(::mlir::AsmParser &odsParser);
  void print(::mlir::AsmPrinter &odsPrinter) const;
  Type getElementType() const;
};
namespace detail {

struct TDMGatherBaseTypeStorage;

} // namespace detail
class TDMGatherBaseType : public ::mlir::Type::TypeBase<TDMGatherBaseType, ::mlir::Type, detail::TDMGatherBaseTypeStorage> {
public:
  using Base::Base;
  static constexpr ::llvm::StringLiteral name = "amdgpu.tdm_gather_base";
  static constexpr ::llvm::StringLiteral dialectName = "amdgpu";
  using Base::getChecked;
  static TDMGatherBaseType get(::mlir::MLIRContext *context, Type elementType, Type indexType);
  static TDMGatherBaseType getChecked(::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError, ::mlir::MLIRContext *context, Type elementType, Type indexType);
  static TDMGatherBaseType get(Type elementType, Type indexType);
  static TDMGatherBaseType getChecked(::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError, Type elementType, Type indexType);
  static ::llvm::LogicalResult verify(::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError, Type elementType, Type indexType);
  static ::llvm::LogicalResult verifyInvariants(::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError, Type elementType, Type indexType);
  static constexpr ::llvm::StringLiteral getMnemonic() {
    return {"tdm_gather_base"};
  }

  static ::mlir::Type parse(::mlir::AsmParser &odsParser);
  void print(::mlir::AsmPrinter &odsPrinter) const;
  Type getElementType() const;
  Type getIndexType() const;
};
class TDMDescriptorType : public ::mlir::Type::TypeBase<TDMDescriptorType, ::mlir::Type, ::mlir::TypeStorage> {
public:
  using Base::Base;
  static constexpr ::llvm::StringLiteral name = "amdgpu.tdm_descriptor";
  static constexpr ::llvm::StringLiteral dialectName = "amdgpu";
  static constexpr ::llvm::StringLiteral getMnemonic() {
    return {"tdm_descriptor"};
  }

};
class DsBarrierStateType : public ::mlir::Type::TypeBase<DsBarrierStateType, ::mlir::Type, ::mlir::TypeStorage, ::mlir::MemRefElementTypeInterface::Trait> {
public:
  using Base::Base;
  static constexpr ::llvm::StringLiteral name = "amdgpu.ds_barrier_state";
  static constexpr ::llvm::StringLiteral dialectName = "amdgpu";
  static constexpr ::llvm::StringLiteral getMnemonic() {
    return {"ds_barrier_state"};
  }

};

} // namespace mlir::amdgpu
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::amdgpu::TDMBaseType)
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::amdgpu::TDMGatherBaseType)
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::amdgpu::TDMDescriptorType)
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::amdgpu::DsBarrierStateType)

#endif // GET_TYPEDEF_CLASSES

