NAME=RISC-V ESIL for arithmetic word instructions
FILE=malloc://1024
CMDS=<<EOF
e asm.arch=riscv
e asm.bits=64
wx 1304500093083000139ff8013308e4413b071801bb030703
aei
6aes
ar a6
ar t2
EOF
EXPECT=<<EOF
0xfffffffe80000005
0xffffffff80000028
EOF
RUN

NAME=RISC-V ESIL for shift word instructions
FILE=malloc://1024
CMDS=<<EOF
e asm.arch=riscv
e asm.bits=64
wx e5267d76359ebb15d6003b57d600bb07b740
aei
6aes
ar a5
EOF
EXPECT=<<EOF
0xffffffffce00007f
EOF
RUN

NAME=RISC-V ESIL for load instructions
FILE=malloc://1024
CMDS=<<EOF
e asm.arch=riscv
e asm.bits=64
wx 37f65aff32e09246036701008317210003081100
aei
aeim
6aes
ar a3
ar a4
ar a5
ar a6
EOF
EXPECT=<<EOF
0x00000000
0xffffffffff5af000
0xffffffffffffff5a
0xfffffffffffffff0
EOF
RUN

NAME=RISC-V ESIL for compressed word instructions
FILE=malloc://1024
CMDS=<<EOF
e asm.arch=riscv
e asm.bits=64
wx 7d76518f1d26319e119f
aei
aeim
5aes
ar a4
EOF
EXPECT=<<EOF
0x00000ff2
EOF
RUN
NAME=riscv64 sraiw sign-extends a word loaded by lw
FILE=malloc://0x100
ARGS=-a riscv -b 64
CMDS=<<EOF
wx 83250500 1bd51540
ar a0=0x80
wv4 0x80000000 @ 0x80
aei
aeip
aes
ar a1
aes
ar a0
EOF
EXPECT=<<EOF
0x80000000
0xffffffffc0000000
EOF
RUN

NAME=riscv64 sraw masks the shift and sign-extends the low word
FILE=malloc://0x100
ARGS=-a riscv -b 64
CMDS=<<EOF
wx 3bd5c540
ar a1=0x80000000
ar a2=0x21
aei
aeip
aes
ar a0
ar a1=0x40000000
ar pc=0
aes
ar a0
EOF
EXPECT=<<EOF
0xffffffffc0000000
0x20000000
EOF
RUN
