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test Entity Reference

test entity More...

Libraries

ieee 

Use Clauses

std_logic 

Ports

clk   in std_logic
 clock input
reset   in std_logic
 active high reste
data_in   in std_logic_vector ( 7 downto 0 )
 input data
data_out   in std_logic_vector ( 7 downto 0 )
 output data

Detailed Description

test entity

test enitity description


The documentation for this class was generated from the following file: