Encoder Module Reference


Port List

output logic [3:0] result
 4 bit result
input logic [15:0] in
 16-bit input
input logic enable
 enable signal

Always Blocks

always_comb encoder_comb
 This comb does not have a name, so one is given to it by Doxygen, based on its line number.

Detailed Description

Definition at line 33 of file Encoder.sv.


Field Documentation

output logic [3:0] Encoder::result

4 bit result

Definition at line 34 of file Encoder.sv.

input logic [15:0] Encoder::in

16-bit input

Definition at line 35 of file Encoder.sv.

input logic Encoder::enable

enable signal

Definition at line 36 of file Encoder.sv.

always_comb Encoder::encoder_comb

This comb does not have a name, so one is given to it by Doxygen, based on its line number.

Definition at line 41 of file Encoder.sv.


The documentation for this module was generated from the following file:
Generated on Thu Aug 14 17:17:35 2008 for ExampleProjects by  doxygen 1.5.2-SystemVerilog-20080806