Doxygen SystemVerilog Example Project

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Intro

This is an example on how to document SystemVerilog with Doxygen. Do not expect this example to produce useful output of any sort...

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License

Doxygen is copyright 1997-2008 by Dimitri van Heesch.

Permission to use, copy, modify, and distribute this software and its documentation under the terms of the GNU General Public License is hereby granted. No representations are made about the suitability of this software for any purpose. It is provided "as is" without express or implied warranty. See the GNU General Public License for more details.

Documents produced by doxygen are derivative works derived from the input used in their production; they are not affected by this license.

This SystemVerilog version of Doxygen has been developed by Nordic Semiconductor ASA, based on Dimitri van Heesch's work.


Generated on Thu Aug 14 17:17:30 2008 for ExampleProjects by  doxygen 1.5.2-SystemVerilog-20080806