Gateclock Module Reference

Reducing the clock. Very bad indeed. More...

Hierarchy diagram for Gateclock:

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Port List

input logic ckin
input logic reset_N
output logic ckout

Always Blocks

always_ff @(posedge ckin or
negedge reset_N
always_noname10
 The module it self.

Detailed Description

Reducing the clock. Very bad indeed.

Definition at line 3 of file Gateclock.sv.


Field Documentation

input logic Gateclock::ckin

Definition at line 4 of file Gateclock.sv.

input logic Gateclock::reset_N

Definition at line 5 of file Gateclock.sv.

output logic Gateclock::ckout

Definition at line 7 of file Gateclock.sv.

always_ff @ ( posedge ckin or negedge reset_N ) Gateclock::always_noname10

The module it self.

Definition at line 10 of file Gateclock.sv.


The documentation for this module was generated from the following file:
Generated on Thu Aug 14 17:17:35 2008 for ExampleProjects by  doxygen 1.5.2-SystemVerilog-20080806