test_Top Module Reference

This module tests the Top module. More...

Hierarchy diagram for test_Top:

Top Gateclock Counter Decoder Decoder

Sub Modules

Top u_Top
 Top instantiation.

Always Blocks

always always_noname9
 Simgple clock generator.

Initial Blocks

initial always_noname15
 Test bench.

Variables

logic ck
 The clock.
logic reset_N
 Reset signal. Active low.
logic [31:0] result
 Result is stored here.

Detailed Description

This module tests the Top module.

Definition at line 2 of file test_Top.sv.


Field Documentation

logic test_Top::ck

The clock.

Definition at line 2 of file test_Top.sv.

logic test_Top::reset_N

Reset signal. Active low.

Definition at line 5 of file test_Top.sv.

logic [31:0] test_Top::result

Result is stored here.

Definition at line 6 of file test_Top.sv.

always test_Top::always_noname9

Simgple clock generator.

Definition at line 9 of file test_Top.sv.

initial test_Top::always_noname15

Test bench.

Definition at line 15 of file test_Top.sv.

Top test_Top::u_Top

Top instantiation.

Definition at line 25 of file test_Top.sv.


The documentation for this module was generated from the following file:
Generated on Thu Aug 14 17:17:35 2008 for ExampleProjects by  doxygen 1.5.2-SystemVerilog-20080806