Hierarchy diagram for test_Top:
Sub Modules | |
Top | u_Top |
Top instantiation. | |
Always Blocks | |
always | always_noname9 |
Simgple clock generator. | |
Initial Blocks | |
initial | always_noname15 |
Test bench. | |
Variables | |
logic | ck |
The clock. | |
logic | reset_N |
Reset signal. Active low. | |
logic [31:0] | result |
Result is stored here. |
Definition at line 2 of file test_Top.sv.
always test_Top::always_noname9 |
initial test_Top::always_noname15 |