Hierarchy diagram for Decoder:
Port List | |
input logic [3:0] | in |
4 bit binary input | |
output logic [15:0] | result |
16-bit result | |
output logic | sync |
Output from the very nice sync thingy. | |
input logic | enable |
Enable for the decoder. | |
Always Blocks | |
always_comb | decoder_comb |
This module implements some random stuff. | |
Assigns | |
assign | assign11 |
This is a strange sync signal that might be useful. |
Definition at line 4 of file Decoder.sv.
always_comb Decoder::decoder_comb |