Top Module Reference

The design's top module is defined here This module uses a generate to create WIDTH/8 instances of Counter. More...

Hierarchy diagram for Top:

test_Top Gateclock Counter Decoder Decoder

Includes

`include Top_Parameters.sv

Sub Modules

Gateclock u_Gateclock
 Initiating the clock reducing module.
Counter u_Counter
Decoder u_decoderLow
Decoder u_decoderHigh

Parameters

parameter ID_CONFIG
 Address. By default set to 0x00.
parameter RV_CONFIG
 Reset value. By default set to 0000 0001.

Variables

input logic ck
input input logic reset_N
input output logic [31:0] result
logic [7:0] counter
 Counter result out.
logic [15:0] encoded
 Counter result encoded.
logic coderenable
 Enable coder.
logic ckhalf
 Internal signal, the output from Gateglock. This clock is reduced by 50%.
Random signals
logic syncHigh
 An output from Decoder. Not sure what to do with it.
logic syncLow
 An output from Decoder.

Detailed Description

The design's top module is defined here This module uses a generate to create WIDTH/8 instances of Counter.

Definition at line 36 of file Top.sv.


Field Documentation

parameter Top::ID_CONFIG

Address. By default set to 0x00.

Definition at line 38 of file Top.sv.

parameter Top::RV_CONFIG

Reset value. By default set to 0000 0001.

Definition at line 39 of file Top.sv.

input logic Top::ck

Definition at line 42 of file Top.sv.

input input logic Top::reset_N

Definition at line 43 of file Top.sv.

input output logic [31:0] Top::result

Definition at line 45 of file Top.sv.

logic [7:0] Top::counter

Counter result out.

Definition at line 45 of file Top.sv.

logic [15:0] Top::encoded

Counter result encoded.

Definition at line 48 of file Top.sv.

logic Top::coderenable

Enable coder.

Definition at line 49 of file Top.sv.

logic Top::ckhalf

Internal signal, the output from Gateglock. This clock is reduced by 50%.

Definition at line 50 of file Top.sv.

logic Top::syncHigh

An output from Decoder. Not sure what to do with it.

Definition at line 54 of file Top.sv.

logic Top::syncLow

An output from Decoder.

Not sure what to do with this either

Definition at line 55 of file Top.sv.

`include Top::Top_Parameters.sv

Definition at line 59 of file Top.sv.

Gateclock Top::u_Gateclock

Initiating the clock reducing module.

Does some important things and returns something else. Even more description is written here. In this very line.

Definition at line 74 of file Top.sv.

Counter Top::u_Counter

Definition at line 80 of file Top.sv.

Decoder Top::u_decoderLow

Definition at line 86 of file Top.sv.

Decoder Top::u_decoderHigh

Definition at line 93 of file Top.sv.


The documentation for this module was generated from the following file:
Generated on Thu Aug 14 17:17:36 2008 for ExampleProjects by  doxygen 1.5.2-SystemVerilog-20080806