00001 00003 module Gateclock( 00004 input logic ckin, 00005 input logic reset_N, 00006 output logic ckout 00007 ); 00008 00010 always_ff @(posedge ckin or negedge reset_N) begin 00011 reg diff; 00012 if (~reset_N) begin 00013 ckout <= 0; 00014 diff <= 0; 00015 end 00016 else begin 00017 diff <= ~diff; 00018 if (diff) 00019 ckout <= ~ckout; 00020 end 00021 end 00022 00023 endmodule : Gateclock