Counter.sv

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00001 
00049 module Counter 
00050 (
00051   output reg [7:0] count,       
00052 
00056   input ck,
00057   input reset_N                 
00058 );
00059 
00065 function [7:0] increment (input [7:0] val);              
00066 reg [3:0] i;                                             
00067 reg carry;                                                
00068   begin
00069     increment = val;
00070     carry = 1'b1;
00071     for (i = 4'b0; ((carry == 4'b1) || (i <= 7));  i = i + 4'b1)
00072        begin
00073          increment[i] = val[i] ^ carry;       // A normal Verilog comment
00074          carry = val[i] & carry;              
00075        end
00076   end       
00077 endfunction
00078 
00083 always_ff @ (posedge ck or negedge reset_N) begin: counter 
00084   if (~reset_N)
00085      count <= 8'h00;
00086   else
00087      count <= increment(count); 
00088 end
00089 
00090 endmodule

Generated on Tue Aug 5 16:13:54 2008 for Tell by  doxygen 1.5.2-SystemVerilog-20.06.2008