00001 /********************************************************************************* 00002 * 00003 * Nordic Semiconductor ASA, Vestre Rosten 81, N-7075 TILLER, NORWAY 00004 * 00005 ********************************************************************************* 00006 * Project name : nrf4352 00007 * Project number : 1154352 00008 * File type : rtl 00009 * @author Markus Bakka Hjertø 00010 * Designers ver : $Id: Top.sv 28 2008-01-30 14:03:27Z nvlsi\mbh $ 00011 * Description : Delayed output clock by 50% 00012 * Last fetched from repository location: 00013 * $URL: http://svn.nordicsemi.no/devmethod/mbh/DoxygenProject/Top/hdl/Top.sv $ 00014 * 00015 * SU : Jan Frode Lønnum (mailto:jfl@nordicsemi.no) 00016 * SU version : default_module.v,v 1.1 2001-09-07 00:07:53+02 rh Exp 00017 * DK release : dk_X.X.X 00018 * Installed date : Wed 29.11.2006 at 18:02:05 00019 * 00020 * Copyright (c) 2006 by Nordic Semiconductor ASA 00021 ********************************************************************************/ 00022 00023 module Gateclock( 00024 input logic ckin, 00025 input logic reset_N, 00026 output logic ckout 00027 ); 00028 00029 always_ff @(posedge ckin or negedge reset_N) begin 00030 reg diff; 00031 if (~reset_N) begin 00032 ckout <= 0; 00033 diff <= 0; 00034 end 00035 else begin 00036 diff <= ~diff; 00037 if (diff) 00038 ckout <= ~ckout; 00039 end 00040 end 00041 00042 endmodule : Gateclock