test_Top.sv

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00001 /*********************************************************************************
00002  *                                                                                 
00003  *        Nordic Semiconductor ASA, Vestre Rosten 81, N-7075 TILLER, NORWAY        
00004  *                                                                                 
00005  *********************************************************************************
00006  *  Project name   : nrf4352                                                       
00007  *  Project number : 1154352                                                       
00008  *  File type      : rtl/testbench                                                  
00009  *  @author          Markus Bakka Hjertø                            
00010  *  Designers ver  : $Id: Top.sv 60 2008-02-07 16:26:06Z nvlsi\mbh $
00011  *  Description    : test_Top
00012  *  Last fetched from repository location:
00013  *  $URL: http://svn.nordicsemi.no/devmethod/mbh/DoxygenProject/Top/hdl/Top.sv $
00014  *
00015  *  SU             : Jan Frode Lønnum  (mailto:jfl@nordicsemi.no)                  
00016  *  SU version     : default_module.v,v 1.1 2001-09-07 00:07:53+02 rh Exp          
00017  *  DK release     : dk_X.X.X                                                       
00018  *  Installed date : Wed 29.11.2006 at 18:02:05                                    
00019  *                   
00020  *                Copyright (c) 2006 by Nordic Semiconductor ASA
00021  ********************************************************************************/
00022 
00023 module test_Top();
00024 
00025   parameter WIDTH=32;
00026   
00027   logic ck;      
00028   logic reset_N;            
00029   logic[WIDTH-1:0] fullresult; 
00030   
00031   // Built in test bench start
00032   always begin
00033     #(100);             
00034     ck = ~ck;  
00035   end
00036   initial begin
00037     ck = 0;
00038     reset_N = 0; 
00039     @(posedge ck);
00040     @(posedge ck);    
00041     reset_N = 1;    
00042   end
00043   // Built in test bench end
00044 
00048  Top #(WIDTH) u_Top(
00049   .ck         (ck),
00050   .reset_N    (reset_N),
00051   .fullresult (fullresult)
00052   ); 
00053  
00054 endmodule : test_Top
00055 
00056 
00057    

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