Hierarchy diagram for Top:
Includes | |
`include | Top_Parameters.sv |
Sub Modules | |
Gateclock | u_Gateclock |
Initiating the clock reducing module. | |
Counter | u_Counter |
Decoder | u_decoderLow |
Decoder | u_decoderHigh |
Parameters | |
parameter | ID_CONFIG |
Address. By default set to 0x00. | |
parameter | RV_CONFIG |
Reset value. By default set to 0000 0001. | |
Variables | |
input logic | ck |
input input logic | reset_N |
input output logic [31:0] | result |
logic [7:0] | counter |
Counter result out. | |
logic [15:0] | encoded |
Counter result encoded. | |
logic | coderenable |
Enable coder. | |
logic | ckhalf |
Internal signal, the output from Gateglock. This clock is reduced by 50%. | |
Random signals | |
logic | syncHigh |
An output from Decoder. Not sure what to do with it. | |
logic | syncLow |
An output from Decoder. |
Definition at line 36 of file Top.sv.
logic Top::coderenable |