Decoder.sv

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00010 module Decoder (
00011 input  wire [3:0]  binary_in   , 
00012 output reg  [15:0] decoder_out , 
00013 output wire        sync,
00014 input  wire        enable        
00015 );
00016 
00017 assign sync = decoder_out[0] || (decoder_out[1] && decoder_out[2]); 
00018 
00019 always_comb 
00020 begin 
00021   decoder_out = 0;
00022   if (enable) begin
00023     case (binary_in)
00024       4'h0 : decoder_out = 16'h0001; // Fixme
00025       4'h1 : decoder_out = 16'h0002;
00026       4'h2 : decoder_out = 16'h0004;
00027       4'h3 : decoder_out = 16'h0008;
00028       4'h4 : decoder_out = 16'h0010;
00029       4'h5 : decoder_out = 16'h0020;
00030       4'h6 : decoder_out = 16'h0040;
00031       4'h7 : decoder_out = 16'h0080;
00032       4'h8 : decoder_out = 16'h0100;
00033       4'h9 : decoder_out = 16'h0200;
00034       4'hA : decoder_out = 16'h0400;
00035       4'hB : decoder_out = 16'h0800;
00036       4'hC : decoder_out = 16'h1000;
00037       4'hD : decoder_out = 16'h2000;
00038       4'hE : decoder_out = 16'h4000;
00039       4'hF : decoder_out = 16'h8000;
00040     endcase
00041   end
00042 end : myalways
00043 
00044 endmodule
00045 

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