Decoder Module Reference

This is a decoder module. More...

Hierarchy diagram for Decoder:

Top test_Top

Port List

input logic [3:0] in
 4 bit binary input
output logic [15:0] result
 16-bit result
output logic sync
 Output from the very nice sync thingy.
input logic enable
 Enable for the decoder.

Always Blocks

always_comb decoder_comb
 This module implements some random stuff.

Assigns

assign assign11
 This is a strange sync signal that might be useful.

Detailed Description

This is a decoder module.

Definition at line 4 of file Decoder.sv.


Field Documentation

input logic [3:0] Decoder::in

4 bit binary input

Definition at line 5 of file Decoder.sv.

output logic [15:0] Decoder::result

16-bit result

Definition at line 6 of file Decoder.sv.

output logic Decoder::sync

Output from the very nice sync thingy.

Definition at line 7 of file Decoder.sv.

input logic Decoder::enable

Enable for the decoder.

Definition at line 8 of file Decoder.sv.

assign Decoder::assign11

This is a strange sync signal that might be useful.

Definition at line 11 of file Decoder.sv.

always_comb Decoder::decoder_comb

This module implements some random stuff.

Definition at line 14 of file Decoder.sv.


The documentation for this module was generated from the following file:
Generated on Thu Aug 14 17:17:34 2008 for ExampleProjects by  doxygen 1.5.2-SystemVerilog-20080806