Processes | |
PROCESS_10 | ( clk ) |
Signals | |
rdadr | std_logic_vector ( 7 downto 0 ) |
wradr | std_logic_vector ( 7 downto 0 ) |
dav | std_logic |
toggle | std_logic |
dp_end | integer range 0 to 127 |
dp_adr | integer range 0 to 127 |
Components | |
frame_buffer |
PROCESS_10 | ( | clk ) |
frame_buffer [Component] |
rdadr std_logic_vector ( 7 downto 0 ) [Signal] |
wradr std_logic_vector ( 7 downto 0 ) [Signal] |
dav std_logic [Signal] |
toggle std_logic [Signal] |
dp_end integer range 0 to 127 [Signal] |
dp_adr integer range 0 to 127 [Signal] |
fb PORT [Port Map] |