00001 ///////////////////////////////////////////////////////////////////// 00002 //// //// 00003 //// Mini-RISC-1 //// 00004 //// Primitives //// 00005 //// //// 00006 //// //// 00007 //// Author: Rudolf Usselmann //// 00008 //// rudi@asics.ws //// 00009 //// //// 00010 //// //// 00011 //// D/L from: http://www.opencores.org/cores/minirisc/ //// 00012 //// //// 00013 ///////////////////////////////////////////////////////////////////// 00014 //// //// 00015 //// Copyright (C) 2000-2002 Rudolf Usselmann //// 00016 //// www.asics.ws //// 00017 //// rudi@asics.ws //// 00018 //// //// 00019 //// This source file may be used and distributed without //// 00020 //// restriction provided that this copyright statement is not //// 00021 //// removed from the file and that any derivative work contains //// 00022 //// the original copyright notice and the associated disclaimer.//// 00023 //// //// 00024 //// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// 00025 //// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// 00026 //// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// 00027 //// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// 00028 //// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// 00029 //// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// 00030 //// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// 00031 //// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// 00032 //// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// 00033 //// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// 00034 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// 00035 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// 00036 //// POSSIBILITY OF SUCH DAMAGE. //// 00037 //// //// 00038 ///////////////////////////////////////////////////////////////////// 00039 00040 // CVS Log 00041 // 00042 // $Id: primitives.v,v 1.3 2002/10/01 12:44:24 rudi Exp $ 00043 // 00044 // $Date: 2002/10/01 12:44:24 $ 00045 // $Revision: 1.3 $ 00046 // $Author: rudi $ 00047 // $Locker: $ 00048 // $State: Exp $ 00049 // 00050 // Change History: 00051 // $Log: primitives.v,v $ 00052 // Revision 1.3 2002/10/01 12:44:24 rudi 00053 // Tweaked code a bit - trying to get it run faster ... 00054 // 00055 // Revision 1.2 2002/09/27 15:35:40 rudi 00056 // Minor update to newer devices ... 00057 // 00058 // 00059 // 00060 // 00061 // 00062 // 00063 // 00064 // 00065 // 00066 // 00067 // 00068 00069 `timescale 1ns / 10ps 00070 00071 // Mux 4:1 8 bits wide 00072 module mux4_8(sel, in0, in1, in2, in3, out); 00073 input [1:0] sel; 00074 input [7:0] in0, in1, in2, in3; 00075 output [7:0] out; 00076 00077 reg [7:0] out; 00078 00079 always @(sel or in0 or in1 or in2 or in3) 00080 case(sel) // synopsys full_case parallel_case 00081 0: out = in0; 00082 1: out = in1; 00083 2: out = in2; 00084 3: out = in3; 00085 endcase 00086 00087 endmodule 00088 00089 // 8 bit comparator 00090 module cmp8_eq(a,b,eq); 00091 input [7:0] a,b; 00092 output eq; 00093 00094 assign eq = (a==b); 00095 00096 endmodule 00097 00098 // MUX 2:1 7 bits wide 00099 module mux2_7(sel, in0, in1, out); 00100 input sel; 00101 input [6:0] in0, in1; 00102 output [6:0] out; 00103 00104 assign out = sel ? in1 : in0; 00105 00106 endmodule 00107 00108 // Mux 8:1 1 bit wide 00109 module mux8_1( sel, in, out); 00110 input [2:0] sel; 00111 input [7:0] in; 00112 output out; 00113 00114 assign out = in[sel]; 00115 00116 endmodule 00117 00118 // Mux 2:1 8 bits wide 00119 module mux2_8(sel, in0, in1, out); 00120 input sel; 00121 input [7:0] in0, in1; 00122 output [7:0] out; 00123 00124 assign out = sel ? in1 : in0; 00125 00126 endmodule 00127 00128 // Mux 8:1 8 bits wide 00129 module mux8_8(sel, in0, in1, in2, in3, in4, in5, in6, in7, out); 00130 input [2:0] sel; 00131 input [7:0] in0, in1, in2, in3, in4, in5, in6, in7; 00132 output [7:0] out; 00133 00134 reg [7:0] out; 00135 00136 always @(sel or in0 or in1 or in2 or in3 or in4 or in5 or in6 or in7) 00137 case(sel) // synopsys full_case parallel_case 00138 3'd0: out = in0; 00139 3'd1: out = in1; 00140 3'd2: out = in2; 00141 3'd3: out = in3; 00142 3'd4: out = in4; 00143 3'd5: out = in5; 00144 3'd6: out = in6; 00145 3'd7: out = in7; 00146 endcase 00147 00148 endmodule 00149 00150 // Mux 2:1 11 bits wide 00151 module mux2_11(sel, in0, in1, out); 00152 input sel; 00153 input [10:0] in0, in1; 00154 output [10:0] out; 00155 00156 assign out = sel ? in1 : in0; 00157 00158 endmodule 00159 00160 00161 // 8bit Add/Sub with carry/borrow out 00162 module add_sub8_co(sub, opa, opb, out, co); 00163 input sub; 00164 input [7:0] opa, opb; 00165 output [7:0] out; 00166 output co; 00167 00168 assign {co, out} = sub ? (opa - opb) : (opa + opb); 00169 00170 endmodule 00171 00172 // 11 bit incrementer 00173 module inc11(in, out); 00174 input [10:0] in; 00175 output [10:0] out; 00176 00177 assign out = in + 11'h1; 00178 00179 endmodule 00180 00181 // 8 bit incrementer 00182 module inc8(in, out); 00183 input [7:0] in; 00184 output [7:0] out; 00185 00186 assign out = in + 8'h1; 00187 00188 endmodule 00189 00190 // A Basic Synchrounous FIFO (4 entries deep) 00191 module sfifo4x11(clk, push, din, pop, dout); 00192 input clk; 00193 input push; 00194 input [10:0] din; 00195 input pop; 00196 output [10:0] dout; 00197 00198 reg [10:0] stack1, stack2, stack3, stack4; 00199 00200 assign dout = stack1; 00201 00202 always @(posedge clk) 00203 begin 00204 if(push) // PUSH stack 00205 begin 00206 stack4 <= #1 stack3; 00207 stack3 <= #1 stack2; 00208 stack2 <= #1 stack1; 00209 stack1 <= #1 din; 00210 end 00211 if(pop) // POP stack 00212 begin 00213 stack1 <= #1 stack2; 00214 stack2 <= #1 stack3; 00215 stack3 <= #1 stack4; 00216 end 00217 end 00218 00219 endmodule 00220 00221