mux4_8 Module Reference

Inheritance diagram for mux4_8:

alu mrisc mrisc_top

List of all members.

Processes

ALWAYS_8  ( sel , in0 , in1 , in2 , in3 )

Ports

sel 
in0 
in1 
in2 
in3 
out 
sel 
in0 
in1 
in2 
in3 
out 

Includes

C_ADDSUB_V1_0
C_MUX_BUS_V1_0
C_COMPARE_V1_0
C_MUX_BIT_V1_0
C_MEM_DP_BLOCK_V1_0
C_REG_FD_V1_0

Inputs

sel [ 1 : 0 ]
in0 [ 7 : 0 ]
in1 [ 7 : 0 ]
in2 [ 7 : 0 ]
in3 [ 7 : 0 ]
sel [ 1 : 0 ]
in0 [ 7 : 0 ]
in1 [ 7 : 0 ]
in2 [ 7 : 0 ]
in3 [ 7 : 0 ]

Outputs

out [ 7 : 0 ]
out [ 7 : 0 ]

Registers

out  [ 7 : 0 ]

Components

u0 xilinx_mux4_8


Detailed Description

Definition at line 72 of file primitives.v.


Member Function Documentation

[Processes]
ALWAYS_8 ( sel ,
in0 ,
in1 ,
in2 ,
in3 )

Definition at line 79 of file primitives.v.

 
00079 always @(sel or in0 or in1 or in2 or in3)
00080         case(sel)       // synopsys full_case parallel_case
00081           0: out = in0;
00082           1: out = in1;
00083           2: out = in2;
00084           3: out = in3;


Member Data Documentation

sel [Ports]

Definition at line 72 of file primitives.v.

in0 [Ports]

Definition at line 72 of file primitives.v.

in1 [Ports]

Definition at line 72 of file primitives.v.

in2 [Ports]

Definition at line 72 of file primitives.v.

in3 [Ports]

Definition at line 72 of file primitives.v.

out [Ports]

Definition at line 72 of file primitives.v.

sel [ 1 : 0 ] [Inputs]

Definition at line 73 of file primitives.v.

in0 [ 7 : 0 ] [Inputs]

Definition at line 74 of file primitives.v.

in1 [ 7 : 0 ] [Inputs]

Definition at line 74 of file primitives.v.

in2 [ 7 : 0 ] [Inputs]

Definition at line 74 of file primitives.v.

in3 [ 7 : 0 ] [Inputs]

Definition at line 74 of file primitives.v.

out [ 7 : 0 ] [Outputs]

Definition at line 75 of file primitives.v.

out [ 7 : 0 ] [Registers]

Definition at line 77 of file primitives.v.

sel [Ports]

Definition at line 84 of file primitives_xilinx.v.

in0 [Ports]

Definition at line 84 of file primitives_xilinx.v.

in1 [Ports]

Definition at line 84 of file primitives_xilinx.v.

in2 [Ports]

Definition at line 84 of file primitives_xilinx.v.

in3 [Ports]

Definition at line 84 of file primitives_xilinx.v.

out [Ports]

Definition at line 84 of file primitives_xilinx.v.

sel [ 1 : 0 ] [Inputs]

Definition at line 85 of file primitives_xilinx.v.

in0 [ 7 : 0 ] [Inputs]

Definition at line 86 of file primitives_xilinx.v.

in1 [ 7 : 0 ] [Inputs]

Definition at line 86 of file primitives_xilinx.v.

in2 [ 7 : 0 ] [Inputs]

Definition at line 86 of file primitives_xilinx.v.

in3 [ 7 : 0 ] [Inputs]

Definition at line 86 of file primitives_xilinx.v.

out [ 7 : 0 ] [Outputs]

Definition at line 87 of file primitives_xilinx.v.

u0 xilinx_mux4_8 [Components]

Reimplemented in alu, mrisc, and mrisc_top.

Definition at line 90 of file primitives_xilinx.v.

C_ADDSUB_V1_0 include [Includes]

Definition at line 73 of file primitives_xilinx.v.

C_MUX_BUS_V1_0 include [Includes]

Definition at line 74 of file primitives_xilinx.v.

C_COMPARE_V1_0 include [Includes]

Definition at line 75 of file primitives_xilinx.v.

C_MUX_BIT_V1_0 include [Includes]

Definition at line 76 of file primitives_xilinx.v.

C_MEM_DP_BLOCK_V1_0 include [Includes]

Definition at line 77 of file primitives_xilinx.v.

C_REG_FD_V1_0 include [Includes]

Definition at line 78 of file primitives_xilinx.v.


The documentation for this class was generated from the following files:

Generated on Sat Apr 19 14:27:19 2008 by  doxygen 1.5.4-20071103