hdlc_interface.mixed Architecture Reference

Inheritance diagram for hdlc_interface.mixed:

hdlc_interface

List of all members.


Signals

tx_db  std_logic_vector ( 7 DOWNTO 0 )
tx_db_adr  std_logic_vector ( 6 DOWNTO 0 )
tx_db_en  std_logic
tx_db_len  std_logic_vector ( 6 DOWNTO 0 )
tx_db_start  std_logic
tx_db_ready  std_logic
tx_dp  std_logic_vector ( 7 DOWNTO 0 )
tx_dp_av  std_logic
tx_dp_en  std_logic
tx_ds  std_logic
tx_ds_av  std_logic
tx_ds_en  std_logic
tx_dc  std_logic
tx_dc_av  std_logic
tx_dc_en  std_logic
tx_dr  std_logic
tx_dr_en  std_logic
rx_dr  std_logic
rx_dr_en  std_logic
rx_dc  std_logic
rx_dc_en  std_logic
rx_dc_byte  std_logic
rx_dc_flag  std_logic
rx_ds  std_logic
rx_ds_en  std_logic
rx_ds_byte  std_logic
rx_ds_flag  std_logic
rx_ds_crcok  std_logic
rx_dp  std_logic_vector ( 7 DOWNTO 0 )
rx_dp_en  std_logic
rx_dp_flag  std_logic
rx_dp_crcok  std_logic
rx_db  std_logic_vector ( 7 DOWNTO 0 )
rx_db_adr  std_logic_vector ( 6 DOWNTO 0 )
rx_db_len  std_logic_vector ( 7 DOWNTO 0 )
rx_db_av  std_logic
rx_db_ecrc  std_logic
rx_db_eover  std_logic
rx_db_read  std_logic
tx_clk_en  std_logic
rx_clk_en  std_logic
int_rx  std_logic
int_tx  std_logic
wire_error1  std_logic
tx_crcfail  std_logic
rx_link  std_logic
tx_link  std_logic
loopback  std_logic
clock_divisor  std_logic_vector ( 15 DOWNTO 0 )
int_reset  std_logic
tx_led_i  std_logic
rx_led_i  std_logic

Components

rx_manchester  Entity <rx_manchester>
rx_flagging  Entity <rx_flagging>
rx_crc  Entity <rx_crc>
rx_serpar  Entity <rx_serpar>
rx_buffer  Entity <rx_buffer>
tx_manchester  Entity <tx_manchester>
tx_flagging  Entity <tx_flagging>
tx_crc  Entity <tx_crc>
tx_serpar  Entity <tx_serpar>
tx_buffer  Entity <tx_buffer>
clock_divider 
convergence  Entity <convergence>


Member Data Documentation

rx_manchester [Component]

rx_flagging [Component]

rx_crc [Component]

rx_serpar [Component]

rx_buffer [Component]

tx_manchester [Component]

tx_flagging [Component]

tx_crc [Component]

tx_serpar [Component]

tx_buffer [Component]

clock_divider [Component]

convergence [Component]

tx_db std_logic_vector ( 7 DOWNTO 0 ) [Signal]

tx_db_adr std_logic_vector ( 6 DOWNTO 0 ) [Signal]

tx_db_en std_logic [Signal]

tx_db_len std_logic_vector ( 6 DOWNTO 0 ) [Signal]

tx_db_start std_logic [Signal]

tx_db_ready std_logic [Signal]

tx_dp std_logic_vector ( 7 DOWNTO 0 ) [Signal]

tx_dp_av std_logic [Signal]

tx_dp_en std_logic [Signal]

tx_ds std_logic [Signal]

tx_ds_av std_logic [Signal]

tx_ds_en std_logic [Signal]

tx_dc std_logic [Signal]

tx_dc_av std_logic [Signal]

tx_dc_en std_logic [Signal]

tx_dr std_logic [Signal]

tx_dr_en std_logic [Signal]

rx_dr std_logic [Signal]

rx_dr_en std_logic [Signal]

rx_dc std_logic [Signal]

rx_dc_en std_logic [Signal]

rx_dc_byte std_logic [Signal]

rx_dc_flag std_logic [Signal]

rx_ds std_logic [Signal]

rx_ds_en std_logic [Signal]

rx_ds_byte std_logic [Signal]

rx_ds_flag std_logic [Signal]

rx_ds_crcok std_logic [Signal]

rx_dp std_logic_vector ( 7 DOWNTO 0 ) [Signal]

rx_dp_en std_logic [Signal]

rx_dp_flag std_logic [Signal]

rx_dp_crcok std_logic [Signal]

rx_db std_logic_vector ( 7 DOWNTO 0 ) [Signal]

rx_db_adr std_logic_vector ( 6 DOWNTO 0 ) [Signal]

rx_db_len std_logic_vector ( 7 DOWNTO 0 ) [Signal]

rx_db_av std_logic [Signal]

rx_db_ecrc std_logic [Signal]

rx_db_eover std_logic [Signal]

rx_db_read std_logic [Signal]

tx_clk_en std_logic [Signal]

rx_clk_en std_logic [Signal]

int_rx std_logic [Signal]

int_tx std_logic [Signal]

wire_error1 std_logic [Signal]

tx_crcfail std_logic [Signal]

rx_link std_logic [Signal]

tx_link std_logic [Signal]

loopback std_logic [Signal]

clock_divisor std_logic_vector ( 15 DOWNTO 0 ) [Signal]

int_reset std_logic [Signal]

tx_led_i std_logic [Signal]

rx_led_i std_logic [Signal]

c0 PORT [Port Map]

divider PORT [Port Map]

rxm PORT [Port Map]

rxf PORT [Port Map]

rxc PORT [Port Map]

rxs PORT [Port Map]

rxb PORT [Port Map]

txm PORT [Port Map]

txf PORT [Port Map]

txc PORT [Port Map]

txs PORT [Port Map]

txb PORT [Port Map]


The documentation for this class was generated from the following file:

Generated on Sat Apr 19 14:13:50 2008 by  doxygen 1.5.4-20071103