Processes | |
PROCESS_3 | ( clk ) |
Signals | |
dp_adr_slv | std_logic_vector ( 7 downto 0 ) |
rdadr | std_logic_vector ( 7 downto 0 ) |
wradr | std_logic_vector ( 7 downto 0 ) |
int_crcok | std_logic |
wren | std_logic |
toggle | std_logic |
dp_adr | integer RANGE 0 TO 129 |
db_read_old | boolean |
full | boolean |
Components | |
frame_buffer |
PROCESS_3 | ( | clk ) |
frame_buffer [Component] |
dp_adr_slv std_logic_vector ( 7 downto 0 ) [Signal] |
rdadr std_logic_vector ( 7 downto 0 ) [Signal] |
wradr std_logic_vector ( 7 downto 0 ) [Signal] |
int_crcok std_logic [Signal] |
wren std_logic [Signal] |
toggle std_logic [Signal] |
dp_adr integer RANGE 0 TO 129 [Signal] |
db_read_old boolean [Signal] |
full boolean [Signal] |
fb PORT [Port Map] |