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Header for MAX7456 driver. More...
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Defines | |
#define | CVPORT PORTD |
#define | CVDDR DDRD |
#define | CVPINR PIND |
#define | CVPORTPIN PORTD2 |
#define | CVDD DDD2 |
#define | CVPIN PIND2 |
#define | VSYNC_vect PCINT0_vect |
#define | VSYNCPORT PORTB |
#define | VSYNCDDR DDRB |
#define | VSYNCPINR PINB |
#define | VSYNCPORTPIN PORTB0 |
#define | VSYNCDD DDB0 |
#define | VSYNCPIN PINB0 |
#define | VSYNCIBIT PCINT0 |
#define | VSYNCMSKREG PCMSK0 |
#define | INIT_MUXS0 |
#define | INIT_OE |
#define | MAXCSPORT PORTB |
#define | MAXCSDDR DDRB |
#define | MAXCSPINR PINB |
#define | MAXCSPIN PB2 |
#define | INITMAX7456 |
#define | ENBL_CVINT |
#define | DSBL_CVINT |
#define | INIT_CV cbi(CVDDR, CVPIN); |
#define | VSYNCINT_ON |
#define | VSYNCINT_OFF |
#define | INIT_VSYNC |
#define | NTSC_LINES 13 |
#define | PAL_LINES 16 |
#define | CHARSPERLN 30 |
#define | REGCNT 10 |
#define | READFLG 0x80 |
#define | SETVAR(var, mask, val) (((uint8_t) var & ~(uint8_t) mask) | ((uint8_t) val & (uint8_t) mask)) |
#define | VM0VSSMSK ((uint8_t) 0x40) |
#define | VSSNTSC ((uint8_t) 0x00) |
#define | VSSPAL ((uint8_t) 0x40) |
#define | VM0SSMMSK ((uint8_t) 0x30) |
#define | SSMAUTO ((uint8_t) 0x00) |
#define | SSMEXT ((uint8_t) 0x20) |
#define | SSMINT ((uint8_t) 0x30) |
#define | VM0DSPMSK ((uint8_t) 0x08) |
#define | DSPOFF ((uint8_t) 0x00) |
#define | DSPON ((uint8_t) 0x08) |
#define | VM0VSMSK ((uint8_t) 0x04) |
#define | VSIMM ((uint8_t) 0x00) |
#define | VSNXT ((uint8_t) 0x04) |
#define | SWRESET ((uint8_t) 0x02) |
#define | VM0VBNMSK ((uint8_t) 0x01) |
#define | DSPENB ((uint8_t) 0x00) |
#define | DSPDIS ((uint8_t) 0x01) |
#define | VM1BCKMSK ((uint8_t) 0x80) |
#define | BCKLOCAL ((uint8_t) 0x00) |
#define | BCKGREY ((uint8_t) 0x80) |
#define | VM1BKMMSK ((uint8_t) 0x70) |
#define | BKM00 ((uint8_t) 0x00) |
#define | BKM07 ((uint8_t) 0x10) |
#define | BKM14 ((uint8_t) 0x02) |
#define | BKM21 ((uint8_t) 0x30) |
#define | BKM28 ((uint8_t) 0x40) |
#define | BKM35 ((uint8_t) 0x50) |
#define | BKM42 ((uint8_t) 0x60) |
#define | BKM49 ((uint8_t) 0x70) |
#define | VM1BLKMSK ((uint8_t) 0x0C) |
#define | BLINK2 ((uint8_t) 0x00) |
#define | BLINK4 ((uint8_t) 0x04) |
#define | BLINK6 ((uint8_t) 0x08) |
#define | BLINK8 ((uint8_t) 0x0C) |
#define | VM1DTYMSK ((uint8_t) 0x03) |
#define | DUTY11 ((uint8_t) 0x00) |
#define | DUTY12 ((uint8_t) 0x01) |
#define | DUTY13 ((uint8_t) 0x02) |
#define | DUTY31 ((uint8_t) 0x03) |
#define | HOSMASK ((uint8_t) 0x3F) |
#define | HOSLEFT ((uint8_t) 0x00) |
#define | HOSMID ((uint8_t) 0x20) |
#define | HOSRIGHT ((uint8_t) 0x3F) |
#define | VOSMASK ((uint8_t) 0x1F) |
#define | VOSLEFT ((uint8_t) 0x00) |
#define | VOSMID ((uint8_t) 0x10) |
#define | VOSRIGHT ((uint8_t) 0x1F) |
#define | DMMOPMMASK ((uint8_t) 0x40) |
#define | OPM16 ((uint8_t) 0x00) |
#define | OPM8 ((uint8_t) 0x40) |
#define | DMMLBCMASK ((uint8_t) 0x20) |
#define | LBCVIN ((uint8_t) 0x00) |
#define | LBCBKM ((uint8_t) 0x20) |
#define | DMMBLKMASK ((uint8_t) 0x10) |
#define | BLKOFF ((uint8_t) 0x00) |
#define | BLKON ((uint8_t) 0x10) |
#define | DMMINVMASK ((uint8_t) 0x08) |
#define | DMMATTRMSK (DMMLBCMASK | DMMBLKMASK | DMMINVMASK) |
#define | INVOFF ((uint8_t) 0x00) |
#define | INVON ((uint8_t) 0x08) |
#define | DMMCLDMASK ((uint8_t) 0x04) |
#define | CLDOFF ((uint8_t) 0x00) |
#define | CLDON ((uint8_t) 0x04) |
#define | DMMVSCMASK ((uint8_t) 0x02) |
#define | VSCIMDT ((uint8_t) 0x00) |
#define | VSCNEXT ((uint8_t) 0x02) |
#define | DMMAIMMASK ((uint8_t) 0x01) |
#define | AIMDSBL ((uint8_t) 0x00) |
#define | AIMENBL ((uint8_t) 0x01) |
#define | AIMEND ((uint8_t) 0xFF) |
#define | DMAHBSBMASK ((uint8_t) 0x02) |
#define | BSBCHAR ((uint8_t) 0x00) |
#define | BSBATTR ((uint8_t) 0x02) |
#define | DMABIT8MSK ((uint8_t) 0x01) |
#define | CMALBYTMASK ((uint8_t) 0x3F |
#define | STATRSTMSK ((uint8_t) 0x40) |
#define | RESETBUSY ((uint8_t) 0x40) |
#define | RESETRDY ((uint8_t) 0x00) |
#define | STATCMSMSK ((uint8_t) 0x20) |
#define | CMSAVAIL ((uint8_t) 0x00) |
#define | CMSUNAVAIL ((uint8_t) 0x20) |
#define | STATLOSMSK ((uint8_t) 0x04) |
#define | LOSINSYNC ((uint8_t) 0x00) |
#define | LOSNOSYNC ((uint8_t) 0x04) |
#define | STATNTSCMSK ((uint8_t) 0x02) |
#define | NTSCOFF ((uint8_t) 0x00) |
#define | NTSCON ((uint8_t) 0x02) |
#define | STATPALMSK ((uint8_t) 0x01) |
#define | PALOFF ((uint8_t) 0x00) |
#define | PALON ((uint8_t) 0x01) |
#define | OSDBLBLCMSK ((uint8_t) 0x10) |
#define | BLCON ((uint8_t) 0x00) |
#define | BLCOFF ((uint8_t) 0x10) |
#define | SELMAX7456 cbi(MAXCSPORT, MAXCSPIN); |
#define | DESELMAX7456 sbi(MAXCSPORT, MAXCSPIN); |
#define | VSYNC_FLANK PC_FLANK(VSYNCPINR, VSYNCPIN) |
#define | DIFFNDX TIMNDX |
#define | CMBYTES 54 |
#define | BLACKPIXEL 0x00 |
#define | WHITEPIXEL 0x02 |
#define | TRNGRAYPIXEL 0x01 |
#define | LEFTPIXEL 6 |
#define | LMIDPIXEL 4 |
#define | RMIDPIXEL 2 |
#define | RGHTPIXEL 0 |
#define | PIXELMASK 0x03 |
#define | READNVM 0x50 |
#define | WRITENVM 0xA0 |
#define | INIT_MAXSPI |
#define | MAX7456setbits(REG, BITS, MASK) |
Set bits in the MAX7456 registers. | |
Typedefs | |
typedef uint8_t | CMpixels [CMBYTES] |
Enumerations | |
enum | WRREGADDR { VM0W, VM1W, HOSW, VOSW, DMMW, DMAHW, DMALW, DMDIW, CMMW, CMAHW, CMALW, CMDIW, OSDMW, RB0W, RB1W, RB2W, RB3W, RB4W, RB5W, RB6W, RB7W, RB8W, RB9W, RB10W, RB11W, RB12W, RB13W, RB14W, RB15W, OSDBLW = 0x6C } |
enum | RDREGADDR { VM0R = READFLG, VM1R, HOSR, VOSR, DMMR, DMAHR, DMALR, DMDIR, CMMR, CMAHR, CMALR, CMDIR, OSDMR, RB0R, RB1R, RB2R, RB3R, RB4R, RB5R, RB6R, RB7R, RB8R, RB9R, RB10R, RB11R, RB12R, RB13R, RB14R, RB15R, OSDBLR = 0xEC, STATR = 0xA0, DMDOR = 0xB0, CMDOR = 0xC0 } |
enum | PALLINENOS { PALHEADLN = 1, PALINFO1LN = 13, PALINFO2LN = 14, PALTIMELN = 15, PALSPARELN = 2 } |
enum | NTSCLINENOS { NTSCHEADLN = 1, NTSCINFO1LN = 10, NTSCINFO2LN = 11, NTSCTIMELN = 12, NTSCSPARELN = 2 } |
Functions | |
uint8_t | MAX7456read_byte (uint8_t regaddr) |
unsigned int | MAX7456rdCA_CATR (uint8_t regaddr) |
void | MAX7456write_byte (uint8_t val, uint8_t regaddr) |
void | MAX7456_init (void) |
void | MAX7456_ClearDisplay () |
void | MAX7456dsptext (char *text, PGM_P transtab, int8_t attributes, int8_t line, int8_t column) |
void | MAXreadregs (uint8_t *regs) |
void | MAX7456readCM (uint8_t CA, CMpixels *pixels) |
Header for MAX7456 driver.
#define BLACKPIXEL 0x00 |
Pixel types
#define CMALBYTMASK ((uint8_t) 0x3F |
CMAH register, Character memory address, address 0x0A/0x8A
#define DMAHBSBMASK ((uint8_t) 0x02) |
DMAH register, Display memory address high, Address 0x05/0x85
#define DMMOPMMASK ((uint8_t) 0x40) |
DMM register, Display memory mode, Address 0x04/0x84
#define HOSMASK ((uint8_t) 0x3F) |
HOS register bits. Horizontal offset register HOS, Address 0x02/0x82
#define INIT_MAXSPI |
/* Enable SPI, master, CPOL = CPHA = 0, MSB first, Fosc/4 */ \
SPCR = (1 << SPE) | (1 << MSTR); \
SPSR = 0;
#define INIT_VSYNC |
cbi(VSYNCDDR, VSYNCPIN); /* Set as input */ \
VSYNCINT_ON
#define INITMAX7456 |
sbi(MAXCSDDR, MAXCSPIN); /* CS as output */ \
DESELMAX7456
#define MAX7456setbits | ( | REG, | |
BITS, | |||
MASK | |||
) |
MAX7456write_byte(REG ## W, \ (MAX7456read_byte(REG ## R) & ~MASK) | (BITS & MASK))
Set bits in the MAX7456 registers.
[in] | REG | is the register name |
[in] | BITS | are the bits to be changed, they are ANDed with MASK |
[in] | MASK | is the bitmask, bit value 1 where a register bit is to be changed |
#define OSDBLBLCMSK ((uint8_t) 0x10) |
OSDBL register, address 6C/EC
#define READFLG 0x80 |
Read register addresses, name as in datasheet followed by R Read address always has MSB set
#define SELMAX7456 cbi(MAXCSPORT, MAXCSPIN); |
MAX7456 SPI setup is in MAX7456.h
#define STATLOSMSK ((uint8_t) 0x04) |
VSYNC, HSYNC later as needed
#define STATRSTMSK ((uint8_t) 0x40) |
STAT register, read only, address 0xa0
#define VM0VSSMSK ((uint8_t) 0x40) |
VM0 bits, Video mode 0, Address 0x00/0x80
#define VM1BCKMSK ((uint8_t) 0x80) |
VM1 bits, video mode 1, Address 0x01/0x81
#define VOSMASK ((uint8_t) 0x1F) |
VOS Vertical offset register, Address 0x03/0x83
#define VSYNCINT_OFF |
/* Disable VSYNC interrupt */ \
clrbit(VSYNCMSKREG, VSYNCIBIT);
#define VSYNCINT_ON |
/* VSYNC interrupt on */ \ setbit(VSYNCMSKREG, VSYNCIBIT); /* Allow VSYNC pin int */ \ setbit(PCICR, PCIE0);
enum NTSCLINENOS |
Line numbers for NTSC
enum PALLINENOS |
Line numbers for PAL
enum WRREGADDR |
Write register addresses, name as in datasheet followed by W