/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM

namespace llvm {

class MCRegisterClass;
extern const MCRegisterClass ARMMCRegisterClasses[];

namespace ARM {
enum {
  NoRegister,
  APSR = 1,
  APSR_NZCV = 2,
  CPSR = 3,
  FPEXC = 4,
  FPINST = 5,
  FPSCR = 6,
  FPSCR_NZCV = 7,
  FPSID = 8,
  ITSTATE = 9,
  LR = 10,
  PC = 11,
  SP = 12,
  SPSR = 13,
  D0 = 14,
  D1 = 15,
  D2 = 16,
  D3 = 17,
  D4 = 18,
  D5 = 19,
  D6 = 20,
  D7 = 21,
  D8 = 22,
  D9 = 23,
  D10 = 24,
  D11 = 25,
  D12 = 26,
  D13 = 27,
  D14 = 28,
  D15 = 29,
  D16 = 30,
  D17 = 31,
  D18 = 32,
  D19 = 33,
  D20 = 34,
  D21 = 35,
  D22 = 36,
  D23 = 37,
  D24 = 38,
  D25 = 39,
  D26 = 40,
  D27 = 41,
  D28 = 42,
  D29 = 43,
  D30 = 44,
  D31 = 45,
  FPINST2 = 46,
  MVFR0 = 47,
  MVFR1 = 48,
  MVFR2 = 49,
  Q0 = 50,
  Q1 = 51,
  Q2 = 52,
  Q3 = 53,
  Q4 = 54,
  Q5 = 55,
  Q6 = 56,
  Q7 = 57,
  Q8 = 58,
  Q9 = 59,
  Q10 = 60,
  Q11 = 61,
  Q12 = 62,
  Q13 = 63,
  Q14 = 64,
  Q15 = 65,
  R0 = 66,
  R1 = 67,
  R2 = 68,
  R3 = 69,
  R4 = 70,
  R5 = 71,
  R6 = 72,
  R7 = 73,
  R8 = 74,
  R9 = 75,
  R10 = 76,
  R11 = 77,
  R12 = 78,
  S0 = 79,
  S1 = 80,
  S2 = 81,
  S3 = 82,
  S4 = 83,
  S5 = 84,
  S6 = 85,
  S7 = 86,
  S8 = 87,
  S9 = 88,
  S10 = 89,
  S11 = 90,
  S12 = 91,
  S13 = 92,
  S14 = 93,
  S15 = 94,
  S16 = 95,
  S17 = 96,
  S18 = 97,
  S19 = 98,
  S20 = 99,
  S21 = 100,
  S22 = 101,
  S23 = 102,
  S24 = 103,
  S25 = 104,
  S26 = 105,
  S27 = 106,
  S28 = 107,
  S29 = 108,
  S30 = 109,
  S31 = 110,
  D0_D2 = 111,
  D1_D3 = 112,
  D2_D4 = 113,
  D3_D5 = 114,
  D4_D6 = 115,
  D5_D7 = 116,
  D6_D8 = 117,
  D7_D9 = 118,
  D8_D10 = 119,
  D9_D11 = 120,
  D10_D12 = 121,
  D11_D13 = 122,
  D12_D14 = 123,
  D13_D15 = 124,
  D14_D16 = 125,
  D15_D17 = 126,
  D16_D18 = 127,
  D17_D19 = 128,
  D18_D20 = 129,
  D19_D21 = 130,
  D20_D22 = 131,
  D21_D23 = 132,
  D22_D24 = 133,
  D23_D25 = 134,
  D24_D26 = 135,
  D25_D27 = 136,
  D26_D28 = 137,
  D27_D29 = 138,
  D28_D30 = 139,
  D29_D31 = 140,
  Q0_Q1 = 141,
  Q1_Q2 = 142,
  Q2_Q3 = 143,
  Q3_Q4 = 144,
  Q4_Q5 = 145,
  Q5_Q6 = 146,
  Q6_Q7 = 147,
  Q7_Q8 = 148,
  Q8_Q9 = 149,
  Q9_Q10 = 150,
  Q10_Q11 = 151,
  Q11_Q12 = 152,
  Q12_Q13 = 153,
  Q13_Q14 = 154,
  Q14_Q15 = 155,
  Q0_Q1_Q2_Q3 = 156,
  Q1_Q2_Q3_Q4 = 157,
  Q2_Q3_Q4_Q5 = 158,
  Q3_Q4_Q5_Q6 = 159,
  Q4_Q5_Q6_Q7 = 160,
  Q5_Q6_Q7_Q8 = 161,
  Q6_Q7_Q8_Q9 = 162,
  Q7_Q8_Q9_Q10 = 163,
  Q8_Q9_Q10_Q11 = 164,
  Q9_Q10_Q11_Q12 = 165,
  Q10_Q11_Q12_Q13 = 166,
  Q11_Q12_Q13_Q14 = 167,
  Q12_Q13_Q14_Q15 = 168,
  R12_SP = 169,
  R0_R1 = 170,
  R2_R3 = 171,
  R4_R5 = 172,
  R6_R7 = 173,
  R8_R9 = 174,
  R10_R11 = 175,
  D0_D1_D2 = 176,
  D1_D2_D3 = 177,
  D2_D3_D4 = 178,
  D3_D4_D5 = 179,
  D4_D5_D6 = 180,
  D5_D6_D7 = 181,
  D6_D7_D8 = 182,
  D7_D8_D9 = 183,
  D8_D9_D10 = 184,
  D9_D10_D11 = 185,
  D10_D11_D12 = 186,
  D11_D12_D13 = 187,
  D12_D13_D14 = 188,
  D13_D14_D15 = 189,
  D14_D15_D16 = 190,
  D15_D16_D17 = 191,
  D16_D17_D18 = 192,
  D17_D18_D19 = 193,
  D18_D19_D20 = 194,
  D19_D20_D21 = 195,
  D20_D21_D22 = 196,
  D21_D22_D23 = 197,
  D22_D23_D24 = 198,
  D23_D24_D25 = 199,
  D24_D25_D26 = 200,
  D25_D26_D27 = 201,
  D26_D27_D28 = 202,
  D27_D28_D29 = 203,
  D28_D29_D30 = 204,
  D29_D30_D31 = 205,
  D0_D2_D4 = 206,
  D1_D3_D5 = 207,
  D2_D4_D6 = 208,
  D3_D5_D7 = 209,
  D4_D6_D8 = 210,
  D5_D7_D9 = 211,
  D6_D8_D10 = 212,
  D7_D9_D11 = 213,
  D8_D10_D12 = 214,
  D9_D11_D13 = 215,
  D10_D12_D14 = 216,
  D11_D13_D15 = 217,
  D12_D14_D16 = 218,
  D13_D15_D17 = 219,
  D14_D16_D18 = 220,
  D15_D17_D19 = 221,
  D16_D18_D20 = 222,
  D17_D19_D21 = 223,
  D18_D20_D22 = 224,
  D19_D21_D23 = 225,
  D20_D22_D24 = 226,
  D21_D23_D25 = 227,
  D22_D24_D26 = 228,
  D23_D25_D27 = 229,
  D24_D26_D28 = 230,
  D25_D27_D29 = 231,
  D26_D28_D30 = 232,
  D27_D29_D31 = 233,
  D0_D2_D4_D6 = 234,
  D1_D3_D5_D7 = 235,
  D2_D4_D6_D8 = 236,
  D3_D5_D7_D9 = 237,
  D4_D6_D8_D10 = 238,
  D5_D7_D9_D11 = 239,
  D6_D8_D10_D12 = 240,
  D7_D9_D11_D13 = 241,
  D8_D10_D12_D14 = 242,
  D9_D11_D13_D15 = 243,
  D10_D12_D14_D16 = 244,
  D11_D13_D15_D17 = 245,
  D12_D14_D16_D18 = 246,
  D13_D15_D17_D19 = 247,
  D14_D16_D18_D20 = 248,
  D15_D17_D19_D21 = 249,
  D16_D18_D20_D22 = 250,
  D17_D19_D21_D23 = 251,
  D18_D20_D22_D24 = 252,
  D19_D21_D23_D25 = 253,
  D20_D22_D24_D26 = 254,
  D21_D23_D25_D27 = 255,
  D22_D24_D26_D28 = 256,
  D23_D25_D27_D29 = 257,
  D24_D26_D28_D30 = 258,
  D25_D27_D29_D31 = 259,
  D1_D2 = 260,
  D3_D4 = 261,
  D5_D6 = 262,
  D7_D8 = 263,
  D9_D10 = 264,
  D11_D12 = 265,
  D13_D14 = 266,
  D15_D16 = 267,
  D17_D18 = 268,
  D19_D20 = 269,
  D21_D22 = 270,
  D23_D24 = 271,
  D25_D26 = 272,
  D27_D28 = 273,
  D29_D30 = 274,
  D1_D2_D3_D4 = 275,
  D3_D4_D5_D6 = 276,
  D5_D6_D7_D8 = 277,
  D7_D8_D9_D10 = 278,
  D9_D10_D11_D12 = 279,
  D11_D12_D13_D14 = 280,
  D13_D14_D15_D16 = 281,
  D15_D16_D17_D18 = 282,
  D17_D18_D19_D20 = 283,
  D19_D20_D21_D22 = 284,
  D21_D22_D23_D24 = 285,
  D23_D24_D25_D26 = 286,
  D25_D26_D27_D28 = 287,
  D27_D28_D29_D30 = 288,
  NUM_TARGET_REGS 	// 289
};
} // end namespace ARM

// Register classes

namespace ARM {
enum {
  HPRRegClassID = 0,
  SPRRegClassID = 1,
  GPRRegClassID = 2,
  GPRwithAPSRRegClassID = 3,
  SPR_8RegClassID = 4,
  GPRnopcRegClassID = 5,
  rGPRRegClassID = 6,
  tGPRwithpcRegClassID = 7,
  hGPRRegClassID = 8,
  tGPRRegClassID = 9,
  GPRnopc_and_hGPRRegClassID = 10,
  hGPR_and_rGPRRegClassID = 11,
  tcGPRRegClassID = 12,
  tGPR_and_tcGPRRegClassID = 13,
  CCRRegClassID = 14,
  GPRspRegClassID = 15,
  hGPR_and_tGPRwithpcRegClassID = 16,
  hGPR_and_tcGPRRegClassID = 17,
  DPRRegClassID = 18,
  DPR_VFP2RegClassID = 19,
  DPR_8RegClassID = 20,
  GPRPairRegClassID = 21,
  GPRPair_with_gsub_1_in_rGPRRegClassID = 22,
  GPRPair_with_gsub_0_in_tGPRRegClassID = 23,
  GPRPair_with_gsub_0_in_hGPRRegClassID = 24,
  GPRPair_with_gsub_0_in_tcGPRRegClassID = 25,
  GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 26,
  GPRPair_with_gsub_1_in_tcGPRRegClassID = 27,
  GPRPair_with_gsub_1_in_GPRspRegClassID = 28,
  DPairSpcRegClassID = 29,
  DPairSpc_with_ssub_0RegClassID = 30,
  DPairSpc_with_ssub_4RegClassID = 31,
  DPairSpc_with_dsub_0_in_DPR_8RegClassID = 32,
  DPairSpc_with_dsub_2_in_DPR_8RegClassID = 33,
  DPairRegClassID = 34,
  DPair_with_ssub_0RegClassID = 35,
  QPRRegClassID = 36,
  DPair_with_ssub_2RegClassID = 37,
  DPair_with_dsub_0_in_DPR_8RegClassID = 38,
  QPR_VFP2RegClassID = 39,
  DPair_with_dsub_1_in_DPR_8RegClassID = 40,
  QPR_8RegClassID = 41,
  DTripleRegClassID = 42,
  DTripleSpcRegClassID = 43,
  DTripleSpc_with_ssub_0RegClassID = 44,
  DTriple_with_ssub_0RegClassID = 45,
  DTriple_with_qsub_0_in_QPRRegClassID = 46,
  DTriple_with_ssub_2RegClassID = 47,
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 48,
  DTripleSpc_with_ssub_4RegClassID = 49,
  DTriple_with_ssub_4RegClassID = 50,
  DTripleSpc_with_ssub_8RegClassID = 51,
  DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 52,
  DTriple_with_dsub_0_in_DPR_8RegClassID = 53,
  DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 54,
  DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 55,
  DTriple_with_dsub_1_in_DPR_8RegClassID = 56,
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 57,
  DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID = 58,
  DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 59,
  DTriple_with_dsub_2_in_DPR_8RegClassID = 60,
  DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 61,
  DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 62,
  DTriple_with_qsub_0_in_QPR_8RegClassID = 63,
  DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 64,
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 65,
  DQuadSpcRegClassID = 66,
  DQuadSpc_with_ssub_0RegClassID = 67,
  DQuadSpc_with_ssub_4RegClassID = 68,
  DQuadSpc_with_ssub_8RegClassID = 69,
  DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 70,
  DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 71,
  DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 72,
  DQuadRegClassID = 73,
  DQuad_with_ssub_0RegClassID = 74,
  DQuad_with_ssub_2RegClassID = 75,
  QQPRRegClassID = 76,
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 77,
  DQuad_with_ssub_4RegClassID = 78,
  DQuad_with_ssub_6RegClassID = 79,
  DQuad_with_dsub_0_in_DPR_8RegClassID = 80,
  DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 81,
  DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 82,
  DQuad_with_dsub_1_in_DPR_8RegClassID = 83,
  DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 84,
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 85,
  DQuad_with_dsub_2_in_DPR_8RegClassID = 86,
  DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 87,
  DQuad_with_dsub_3_in_DPR_8RegClassID = 88,
  DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 89,
  DQuad_with_qsub_0_in_QPR_8RegClassID = 90,
  DQuad_with_qsub_1_in_QPR_8RegClassID = 91,
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 92,
  DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 93,
  QQQQPRRegClassID = 94,
  QQQQPR_with_ssub_0RegClassID = 95,
  QQQQPR_with_ssub_4RegClassID = 96,
  QQQQPR_with_ssub_8RegClassID = 97,
  QQQQPR_with_ssub_12RegClassID = 98,
  QQQQPR_with_dsub_0_in_DPR_8RegClassID = 99,
  QQQQPR_with_dsub_2_in_DPR_8RegClassID = 100,
  QQQQPR_with_dsub_4_in_DPR_8RegClassID = 101,
  QQQQPR_with_dsub_6_in_DPR_8RegClassID = 102,

  };
} // end namespace ARM


// Subregister indices

namespace ARM {
enum {
  NoSubRegister,
  dsub_0,	// 1
  dsub_1,	// 2
  dsub_2,	// 3
  dsub_3,	// 4
  dsub_4,	// 5
  dsub_5,	// 6
  dsub_6,	// 7
  dsub_7,	// 8
  gsub_0,	// 9
  gsub_1,	// 10
  qqsub_0,	// 11
  qqsub_1,	// 12
  qsub_0,	// 13
  qsub_1,	// 14
  qsub_2,	// 15
  qsub_3,	// 16
  ssub_0,	// 17
  ssub_1,	// 18
  ssub_2,	// 19
  ssub_3,	// 20
  ssub_4,	// 21
  ssub_5,	// 22
  ssub_6,	// 23
  ssub_7,	// 24
  ssub_8,	// 25
  ssub_9,	// 26
  ssub_10,	// 27
  ssub_11,	// 28
  ssub_12,	// 29
  ssub_13,	// 30
  dsub_7_then_ssub_0,	// 31
  dsub_7_then_ssub_1,	// 32
  ssub_0_ssub_1_ssub_4_ssub_5,	// 33
  ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5,	// 34
  ssub_2_ssub_3_ssub_6_ssub_7,	// 35
  ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7,	// 36
  ssub_2_ssub_3_ssub_4_ssub_5,	// 37
  ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9,	// 38
  ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,	// 39
  ssub_2_ssub_3_ssub_6_ssub_7_dsub_5,	// 40
  ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7,	// 41
  ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,	// 42
  ssub_4_ssub_5_ssub_8_ssub_9,	// 43
  ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,	// 44
  ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,	// 45
  ssub_6_ssub_7_dsub_5,	// 46
  ssub_6_ssub_7_ssub_8_ssub_9_dsub_5,	// 47
  ssub_6_ssub_7_dsub_5_dsub_7,	// 48
  ssub_6_ssub_7_ssub_8_ssub_9,	// 49
  ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13,	// 50
  ssub_8_ssub_9_ssub_12_ssub_13,	// 51
  ssub_8_ssub_9_dsub_5_ssub_12_ssub_13,	// 52
  dsub_5_dsub_7,	// 53
  dsub_5_ssub_12_ssub_13_dsub_7,	// 54
  dsub_5_ssub_12_ssub_13,	// 55
  ssub_4_ssub_5_ssub_6_ssub_7_qsub_2,	// 56
  NUM_TARGET_SUBREGS
};
} // end namespace ARM

} // end namespace llvm

#endif // GET_REGINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC

namespace llvm {

extern const MCPhysReg ARMRegDiffLists[] = {
  /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0,
  /* 91 */ 40, 1, 1, 1, 1, 1, 0,
  /* 98 */ 65196, 1, 1, 1, 1, 1, 0,
  /* 105 */ 40, 1, 1, 1, 1, 0,
  /* 111 */ 42, 1, 1, 1, 1, 0,
  /* 117 */ 42, 1, 1, 1, 0,
  /* 122 */ 64510, 1, 1, 1, 0,
  /* 127 */ 65015, 1, 1, 1, 0,
  /* 132 */ 65282, 1, 1, 1, 0,
  /* 137 */ 65348, 1, 1, 1, 0,
  /* 142 */ 13, 1, 1, 0,
  /* 146 */ 42, 1, 1, 0,
  /* 150 */ 65388, 1, 1, 0,
  /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0,
  /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0,
  /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0,
  /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0,
  /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0,
  /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0,
  /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0,
  /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0,
  /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0,
  /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0,
  /* 254 */ 65489, 133, 65416, 1, 1, 0,
  /* 260 */ 65490, 133, 65416, 1, 1, 0,
  /* 266 */ 65491, 133, 65416, 1, 1, 0,
  /* 272 */ 65492, 133, 65416, 1, 1, 0,
  /* 278 */ 65493, 133, 65416, 1, 1, 0,
  /* 284 */ 65494, 133, 65416, 1, 1, 0,
  /* 290 */ 65495, 133, 65416, 1, 1, 0,
  /* 296 */ 65496, 133, 65416, 1, 1, 0,
  /* 302 */ 65497, 133, 65416, 1, 1, 0,
  /* 308 */ 65498, 133, 65416, 1, 1, 0,
  /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0,
  /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0,
  /* 332 */ 65136, 1, 3, 1, 3, 1, 0,
  /* 339 */ 65326, 1, 3, 1, 0,
  /* 344 */ 13, 1, 0,
  /* 347 */ 14, 1, 0,
  /* 350 */ 65, 1, 0,
  /* 353 */ 65500, 65, 1, 65471, 66, 1, 0,
  /* 360 */ 65291, 66, 1, 65470, 67, 1, 0,
  /* 367 */ 65439, 65, 1, 65472, 67, 1, 0,
  /* 374 */ 65501, 67, 1, 65469, 68, 1, 0,
  /* 381 */ 65439, 66, 1, 65471, 68, 1, 0,
  /* 388 */ 65292, 68, 1, 65468, 69, 1, 0,
  /* 395 */ 65439, 67, 1, 65470, 69, 1, 0,
  /* 402 */ 65502, 69, 1, 65467, 70, 1, 0,
  /* 409 */ 65439, 68, 1, 65469, 70, 1, 0,
  /* 416 */ 65293, 70, 1, 65466, 71, 1, 0,
  /* 423 */ 65439, 69, 1, 65468, 71, 1, 0,
  /* 430 */ 65503, 71, 1, 65465, 72, 1, 0,
  /* 437 */ 65439, 70, 1, 65467, 72, 1, 0,
  /* 444 */ 65294, 72, 1, 65464, 73, 1, 0,
  /* 451 */ 65439, 71, 1, 65466, 73, 1, 0,
  /* 458 */ 65504, 73, 1, 65463, 74, 1, 0,
  /* 465 */ 65439, 72, 1, 65465, 74, 1, 0,
  /* 472 */ 65295, 74, 1, 65462, 75, 1, 0,
  /* 479 */ 65439, 73, 1, 65464, 75, 1, 0,
  /* 486 */ 65505, 75, 1, 65461, 76, 1, 0,
  /* 493 */ 65439, 74, 1, 65463, 76, 1, 0,
  /* 500 */ 65296, 76, 1, 65460, 77, 1, 0,
  /* 507 */ 65439, 75, 1, 65462, 77, 1, 0,
  /* 514 */ 65506, 77, 1, 65459, 78, 1, 0,
  /* 521 */ 65439, 76, 1, 65461, 78, 1, 0,
  /* 528 */ 65297, 78, 1, 65458, 79, 1, 0,
  /* 535 */ 65439, 77, 1, 65460, 79, 1, 0,
  /* 542 */ 65507, 79, 1, 65457, 80, 1, 0,
  /* 549 */ 65439, 78, 1, 65459, 80, 1, 0,
  /* 556 */ 65045, 1, 0,
  /* 559 */ 65260, 1, 0,
  /* 562 */ 65299, 1, 0,
  /* 565 */ 65300, 1, 0,
  /* 568 */ 65301, 1, 0,
  /* 571 */ 65302, 1, 0,
  /* 574 */ 65303, 1, 0,
  /* 577 */ 65304, 1, 0,
  /* 580 */ 65305, 1, 0,
  /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0,
  /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0,
  /* 600 */ 65488, 13, 121, 65416, 1, 0,
  /* 606 */ 65489, 13, 121, 65416, 1, 0,
  /* 612 */ 65490, 13, 121, 65416, 1, 0,
  /* 618 */ 65491, 13, 121, 65416, 1, 0,
  /* 624 */ 65492, 13, 121, 65416, 1, 0,
  /* 630 */ 65493, 13, 121, 65416, 1, 0,
  /* 636 */ 65494, 13, 121, 65416, 1, 0,
  /* 642 */ 65495, 13, 121, 65416, 1, 0,
  /* 648 */ 65496, 13, 121, 65416, 1, 0,
  /* 654 */ 65497, 13, 121, 65416, 1, 0,
  /* 660 */ 65498, 13, 121, 65416, 1, 0,
  /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0,
  /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0,
  /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0,
  /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0,
  /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0,
  /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0,
  /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0,
  /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0,
  /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0,
  /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0,
  /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0,
  /* 765 */ 65488, 133, 65416, 1, 0,
  /* 770 */ 65499, 134, 65416, 1, 0,
  /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0,
  /* 783 */ 65432, 1, 0,
  /* 786 */ 65433, 1, 0,
  /* 789 */ 65434, 1, 0,
  /* 792 */ 65435, 1, 0,
  /* 795 */ 65436, 1, 0,
  /* 798 */ 65437, 1, 0,
  /* 801 */ 65464, 1, 0,
  /* 804 */ 65508, 1, 0,
  /* 807 */ 65509, 1, 0,
  /* 810 */ 65510, 1, 0,
  /* 813 */ 65511, 1, 0,
  /* 816 */ 65512, 1, 0,
  /* 819 */ 65513, 1, 0,
  /* 822 */ 65514, 1, 0,
  /* 825 */ 65515, 1, 0,
  /* 828 */ 65520, 1, 0,
  /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0,
  /* 839 */ 65136, 1, 3, 1, 2, 0,
  /* 845 */ 65326, 1, 2, 0,
  /* 849 */ 65080, 1, 3, 1, 2, 2, 0,
  /* 856 */ 65136, 1, 2, 2, 0,
  /* 861 */ 65080, 1, 2, 2, 2, 0,
  /* 867 */ 65330, 2, 2, 2, 0,
  /* 872 */ 65080, 1, 3, 2, 2, 0,
  /* 878 */ 65358, 2, 2, 0,
  /* 882 */ 65080, 1, 3, 1, 3, 2, 0,
  /* 889 */ 65136, 1, 3, 2, 0,
  /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0,
  /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0,
  /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0,
  /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0,
  /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0,
  /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0,
  /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0,
  /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0,
  /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0,
  /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0,
  /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0,
  /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0,
  /* 1038 */ 65344, 2, 2, 93, 2, 0,
  /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0,
  /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0,
  /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0,
  /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0,
  /* 1080 */ 65439, 2, 0,
  /* 1083 */ 65453, 2, 0,
  /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0,
  /* 1094 */ 65136, 1, 3, 1, 3, 0,
  /* 1100 */ 65326, 1, 3, 0,
  /* 1104 */ 5, 0,
  /* 1106 */ 140, 65486, 13, 0,
  /* 1110 */ 14, 0,
  /* 1112 */ 126, 65501, 15, 0,
  /* 1116 */ 10, 66, 0,
  /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0,
  /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0,
  /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0,
  /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0,
  /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0,
  /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0,
  /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0,
  /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0,
  /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0,
  /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0,
  /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0,
  /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0,
  /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0,
  /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0,
  /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0,
  /* 1359 */ 91, 0,
  /* 1361 */ 98, 0,
  /* 1363 */ 99, 0,
  /* 1365 */ 100, 0,
  /* 1367 */ 101, 0,
  /* 1369 */ 102, 0,
  /* 1371 */ 103, 0,
  /* 1373 */ 104, 0,
  /* 1375 */ 65374, 1, 1, 20, 75, 135, 0,
  /* 1382 */ 65374, 1, 1, 21, 74, 136, 0,
  /* 1389 */ 65374, 1, 1, 22, 73, 137, 0,
  /* 1396 */ 65374, 1, 1, 23, 72, 138, 0,
  /* 1403 */ 65374, 1, 1, 24, 71, 139, 0,
  /* 1410 */ 65374, 1, 1, 25, 70, 140, 0,
  /* 1417 */ 65374, 1, 1, 26, 69, 141, 0,
  /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0,
  /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0,
  /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0,
  /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0,
  /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0,
  /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0,
  /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0,
  /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0,
  /* 1526 */ 157, 0,
  /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0,
  /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0,
  /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0,
  /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0,
  /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0,
  /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0,
  /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0,
  /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0,
  /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0,
  /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0,
  /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0,
  /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0,
  /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0,
  /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0,
  /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0,
  /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0,
  /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0,
  /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0,
  /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0,
  /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0,
  /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0,
  /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0,
  /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0,
  /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0,
  /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0,
  /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0,
  /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0,
  /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0,
  /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0,
  /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0,
  /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0,
  /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0,
  /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0,
  /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0,
  /* 2455 */ 65487, 13, 121, 65416, 0,
  /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0,
  /* 2468 */ 65466, 1, 65486, 133, 65416, 0,
  /* 2474 */ 65487, 133, 65416, 0,
  /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
  /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
  /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0,
  /* 2509 */ 65452, 1, 65500, 134, 65417, 0,
  /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0,
  /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0,
  /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0,
  /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0,
  /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0,
  /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0,
  /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0,
  /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0,
  /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0,
  /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0,
  /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0,
  /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0,
  /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0,
  /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0,
  /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0,
  /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0,
  /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0,
  /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0,
  /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0,
  /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0,
  /* 2832 */ 26, 65446, 92, 65445, 0,
  /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0,
  /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0,
  /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0,
  /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0,
  /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
  /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
  /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0,
  /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0,
  /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
  /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
  /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0,
  /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0,
  /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
  /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
  /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0,
  /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0,
  /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
  /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
  /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
  /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
  /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0,
  /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
  /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
  /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
  /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
  /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0,
  /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
  /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
  /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
  /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
  /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
  /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0,
  /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
  /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
  /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
  /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
  /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
  /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0,
  /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
  /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
  /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
  /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
  /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
  /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0,
  /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
  /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
  /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
  /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
  /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
  /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0,
  /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
  /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
  /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
  /* 3839 */ 65298, 80, 1, 65456, 0,
  /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
  /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
  /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0,
  /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
  /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
  /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0,
  /* 3948 */ 65439, 80, 1, 65457, 0,
  /* 3953 */ 28, 65457, 0,
  /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
  /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
  /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
  /* 4002 */ 26, 65458, 80, 65457, 0,
  /* 4007 */ 65439, 79, 1, 65458, 0,
  /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0,
  /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0,
  /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0,
  /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0,
  /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0,
  /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0,
  /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0,
  /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0,
  /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0,
  /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0,
  /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0,
  /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0,
  /* 4114 */ 65445, 65470, 0,
  /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0,
  /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0,
  /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0,
  /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0,
  /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0,
  /* 4182 */ 65534, 0,
  /* 4184 */ 65535, 0,
};

extern const LaneBitmask ARMLaneMaskLists[] = {
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
  /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
  /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask::getAll(),
  /* 8 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(),
  /* 11 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
  /* 16 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask::getAll(),
  /* 20 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask::getAll(),
  /* 23 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(),
  /* 28 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(),
  /* 35 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
  /* 39 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
  /* 42 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
  /* 48 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
  /* 53 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(),
  /* 57 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask::getAll(),
  /* 66 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000300), LaneBitmask::getAll(),
  /* 74 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
  /* 81 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
  /* 87 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(),
  /* 92 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask::getAll(),
  /* 99 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
  /* 105 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
  /* 110 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(),
  /* 114 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask::getAll(),
  /* 123 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
  /* 131 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
  /* 138 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
  /* 144 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(),
  /* 149 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask(0x00010000), LaneBitmask(0x00020000), LaneBitmask::getAll(),
  /* 166 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
  /* 181 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
  /* 194 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
  /* 205 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(),
};

extern const uint16_t ARMSubRegIdxLists[] = {
  /* 0 */ 1, 2, 0,
  /* 3 */ 1, 17, 18, 2, 0,
  /* 8 */ 1, 3, 0,
  /* 11 */ 1, 17, 18, 3, 0,
  /* 16 */ 9, 10, 0,
  /* 19 */ 17, 18, 0,
  /* 22 */ 1, 17, 18, 2, 19, 20, 0,
  /* 29 */ 1, 17, 18, 3, 21, 22, 0,
  /* 36 */ 1, 2, 3, 13, 33, 37, 0,
  /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0,
  /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0,
  /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0,
  /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0,
  /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0,
  /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
  /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
  /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0,
  /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0,
  /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0,
  /* 188 */ 1, 3, 5, 33, 43, 0,
  /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0,
  /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0,
  /* 212 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43, 0,
  /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0,
  /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0,
  /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0,
  /* 260 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51, 0,
  /* 276 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51, 0,
  /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
  /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
  /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
  /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
  /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
};

extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[] = {
  { 65535, 65535 },
  { 0, 64 },	// dsub_0
  { 64, 64 },	// dsub_1
  { 128, 64 },	// dsub_2
  { 192, 64 },	// dsub_3
  { 256, 64 },	// dsub_4
  { 320, 64 },	// dsub_5
  { 384, 64 },	// dsub_6
  { 448, 64 },	// dsub_7
  { 0, 32 },	// gsub_0
  { 32, 32 },	// gsub_1
  { 0, 256 },	// qqsub_0
  { 256, 256 },	// qqsub_1
  { 0, 128 },	// qsub_0
  { 128, 128 },	// qsub_1
  { 256, 128 },	// qsub_2
  { 384, 128 },	// qsub_3
  { 0, 32 },	// ssub_0
  { 32, 32 },	// ssub_1
  { 64, 32 },	// ssub_2
  { 96, 32 },	// ssub_3
  { 128, 32 },	// ssub_4
  { 160, 32 },	// ssub_5
  { 192, 32 },	// ssub_6
  { 224, 32 },	// ssub_7
  { 256, 32 },	// ssub_8
  { 288, 32 },	// ssub_9
  { 320, 32 },	// ssub_10
  { 352, 32 },	// ssub_11
  { 384, 32 },	// ssub_12
  { 416, 32 },	// ssub_13
  { 448, 32 },	// dsub_7_then_ssub_0
  { 480, 32 },	// dsub_7_then_ssub_1
  { 65535, 128 },	// ssub_0_ssub_1_ssub_4_ssub_5
  { 0, 192 },	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  { 65535, 128 },	// ssub_2_ssub_3_ssub_6_ssub_7
  { 64, 192 },	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  { 64, 128 },	// ssub_2_ssub_3_ssub_4_ssub_5
  { 65535, 192 },	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  { 65535, 256 },	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  { 65535, 192 },	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  { 65535, 256 },	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
  { 64, 256 },	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  { 65535, 128 },	// ssub_4_ssub_5_ssub_8_ssub_9
  { 128, 192 },	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  { 65535, 192 },	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  { 65535, 128 },	// ssub_6_ssub_7_dsub_5
  { 192, 192 },	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  { 65535, 192 },	// ssub_6_ssub_7_dsub_5_dsub_7
  { 192, 128 },	// ssub_6_ssub_7_ssub_8_ssub_9
  { 192, 256 },	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  { 65535, 128 },	// ssub_8_ssub_9_ssub_12_ssub_13
  { 256, 192 },	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  { 65535, 128 },	// dsub_5_dsub_7
  { 320, 192 },	// dsub_5_ssub_12_ssub_13_dsub_7
  { 320, 128 },	// dsub_5_ssub_12_ssub_13
  { 128, 256 },	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

extern const char ARMRegStrings[] = {
  /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
  /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
  /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
  /* 39 */ 'R', '1', '0', 0,
  /* 43 */ 'S', '1', '0', 0,
  /* 47 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
  /* 63 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
  /* 79 */ 'S', '2', '0', 0,
  /* 83 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
  /* 99 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
  /* 115 */ 'S', '3', '0', 0,
  /* 119 */ 'D', '0', 0,
  /* 122 */ 'Q', '0', 0,
  /* 125 */ 'M', 'V', 'F', 'R', '0', 0,
  /* 131 */ 'S', '0', 0,
  /* 134 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
  /* 145 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
  /* 158 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
  /* 172 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
  /* 180 */ 'S', '1', '1', 0,
  /* 184 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
  /* 196 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
  /* 212 */ 'S', '2', '1', 0,
  /* 216 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
  /* 228 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
  /* 244 */ 'S', '3', '1', 0,
  /* 248 */ 'D', '1', 0,
  /* 251 */ 'Q', '0', '_', 'Q', '1', 0,
  /* 257 */ 'M', 'V', 'F', 'R', '1', 0,
  /* 263 */ 'R', '0', '_', 'R', '1', 0,
  /* 269 */ 'S', '1', 0,
  /* 272 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
  /* 286 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
  /* 301 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
  /* 316 */ 'R', '1', '2', 0,
  /* 320 */ 'S', '1', '2', 0,
  /* 324 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
  /* 340 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
  /* 356 */ 'S', '2', '2', 0,
  /* 360 */ 'D', '0', '_', 'D', '2', 0,
  /* 366 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
  /* 375 */ 'Q', '1', '_', 'Q', '2', 0,
  /* 381 */ 'M', 'V', 'F', 'R', '2', 0,
  /* 387 */ 'S', '2', 0,
  /* 390 */ 'F', 'P', 'I', 'N', 'S', 'T', '2', 0,
  /* 398 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
  /* 412 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
  /* 424 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
  /* 440 */ 'S', '1', '3', 0,
  /* 444 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
  /* 460 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
  /* 472 */ 'S', '2', '3', 0,
  /* 476 */ 'D', '1', '_', 'D', '3', 0,
  /* 482 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
  /* 491 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
  /* 503 */ 'R', '2', '_', 'R', '3', 0,
  /* 509 */ 'S', '3', 0,
  /* 512 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
  /* 527 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
  /* 543 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
  /* 559 */ 'S', '1', '4', 0,
  /* 563 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
  /* 579 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
  /* 595 */ 'S', '2', '4', 0,
  /* 599 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
  /* 608 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
  /* 620 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
  /* 632 */ 'R', '4', 0,
  /* 635 */ 'S', '4', 0,
  /* 638 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
  /* 653 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
  /* 665 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
  /* 681 */ 'S', '1', '5', 0,
  /* 685 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
  /* 701 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
  /* 713 */ 'S', '2', '5', 0,
  /* 717 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
  /* 726 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
  /* 735 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
  /* 747 */ 'R', '4', '_', 'R', '5', 0,
  /* 753 */ 'S', '5', 0,
  /* 756 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
  /* 772 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
  /* 788 */ 'S', '1', '6', 0,
  /* 792 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
  /* 808 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
  /* 824 */ 'S', '2', '6', 0,
  /* 828 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
  /* 840 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
  /* 852 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
  /* 864 */ 'R', '6', 0,
  /* 867 */ 'S', '6', 0,
  /* 870 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
  /* 886 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
  /* 898 */ 'S', '1', '7', 0,
  /* 902 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
  /* 918 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
  /* 930 */ 'S', '2', '7', 0,
  /* 934 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
  /* 946 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
  /* 955 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
  /* 967 */ 'R', '6', '_', 'R', '7', 0,
  /* 973 */ 'S', '7', 0,
  /* 976 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
  /* 992 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
  /* 1008 */ 'S', '1', '8', 0,
  /* 1012 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
  /* 1028 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
  /* 1044 */ 'S', '2', '8', 0,
  /* 1048 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
  /* 1060 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
  /* 1072 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
  /* 1084 */ 'R', '8', 0,
  /* 1087 */ 'S', '8', 0,
  /* 1090 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
  /* 1106 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
  /* 1118 */ 'S', '1', '9', 0,
  /* 1122 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
  /* 1138 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
  /* 1150 */ 'S', '2', '9', 0,
  /* 1154 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
  /* 1166 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
  /* 1175 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
  /* 1187 */ 'R', '8', '_', 'R', '9', 0,
  /* 1193 */ 'S', '9', 0,
  /* 1196 */ 'P', 'C', 0,
  /* 1199 */ 'F', 'P', 'E', 'X', 'C', 0,
  /* 1205 */ 'F', 'P', 'S', 'I', 'D', 0,
  /* 1211 */ 'I', 'T', 'S', 'T', 'A', 'T', 'E', 0,
  /* 1219 */ 'R', '1', '2', '_', 'S', 'P', 0,
  /* 1226 */ 'F', 'P', 'S', 'C', 'R', 0,
  /* 1232 */ 'L', 'R', 0,
  /* 1235 */ 'A', 'P', 'S', 'R', 0,
  /* 1240 */ 'C', 'P', 'S', 'R', 0,
  /* 1245 */ 'S', 'P', 'S', 'R', 0,
  /* 1250 */ 'F', 'P', 'I', 'N', 'S', 'T', 0,
  /* 1257 */ 'F', 'P', 'S', 'C', 'R', '_', 'N', 'Z', 'C', 'V', 0,
  /* 1268 */ 'A', 'P', 'S', 'R', '_', 'N', 'Z', 'C', 'V', 0,
};

extern const MCRegisterDesc ARMRegDesc[] = { // Descriptors
  { 12, 0, 0, 0, 0, 0 },
  { 1235, 16, 16, 2, 66945, 0 },
  { 1268, 16, 16, 2, 66945, 0 },
  { 1240, 16, 16, 2, 66945, 0 },
  { 1199, 16, 16, 2, 66945, 0 },
  { 1250, 16, 16, 2, 66945, 0 },
  { 1226, 16, 16, 2, 17664, 0 },
  { 1257, 16, 16, 2, 17664, 0 },
  { 1205, 16, 16, 2, 66913, 0 },
  { 1211, 16, 16, 2, 66913, 0 },
  { 1232, 16, 16, 2, 66913, 0 },
  { 1196, 16, 16, 2, 66913, 0 },
  { 1223, 16, 1526, 2, 66913, 0 },
  { 1245, 16, 16, 2, 66913, 0 },
  { 119, 350, 4013, 19, 13250, 8 },
  { 248, 357, 2479, 19, 13250, 8 },
  { 363, 364, 3957, 19, 13250, 8 },
  { 479, 378, 3845, 19, 13250, 8 },
  { 605, 392, 3893, 19, 13250, 8 },
  { 723, 406, 3724, 19, 13250, 8 },
  { 837, 420, 3780, 19, 13250, 8 },
  { 943, 434, 3604, 19, 13250, 8 },
  { 1057, 448, 3664, 19, 13250, 8 },
  { 1163, 462, 3484, 19, 13250, 8 },
  { 9, 476, 3544, 19, 13250, 8 },
  { 141, 490, 3364, 19, 13250, 8 },
  { 282, 504, 3424, 19, 13250, 8 },
  { 408, 518, 3244, 19, 13250, 8 },
  { 523, 532, 3304, 19, 13250, 8 },
  { 649, 546, 3149, 19, 13250, 8 },
  { 768, 16, 3208, 2, 17761, 0 },
  { 882, 16, 3078, 2, 17761, 0 },
  { 988, 16, 3113, 2, 17761, 0 },
  { 1102, 16, 3008, 2, 17761, 0 },
  { 59, 16, 3043, 2, 17761, 0 },
  { 192, 16, 2938, 2, 17761, 0 },
  { 336, 16, 2973, 2, 17761, 0 },
  { 456, 16, 2868, 2, 17761, 0 },
  { 575, 16, 2903, 2, 17761, 0 },
  { 697, 16, 2797, 2, 17761, 0 },
  { 804, 16, 2837, 2, 17761, 0 },
  { 914, 16, 2363, 2, 17761, 0 },
  { 1024, 16, 2411, 2, 17761, 0 },
  { 1134, 16, 2384, 2, 17761, 0 },
  { 95, 16, 2429, 2, 17761, 0 },
  { 224, 16, 2789, 2, 17761, 0 },
  { 390, 16, 16, 2, 17761, 0 },
  { 125, 16, 16, 2, 17761, 0 },
  { 257, 16, 16, 2, 17761, 0 },
  { 381, 16, 16, 2, 17761, 0 },
  { 122, 353, 1112, 22, 2196, 11 },
  { 254, 374, 775, 22, 2196, 11 },
  { 378, 402, 314, 22, 2196, 11 },
  { 500, 430, 244, 22, 2196, 11 },
  { 629, 458, 234, 22, 2196, 11 },
  { 744, 486, 224, 22, 2196, 11 },
  { 861, 514, 214, 22, 2196, 11 },
  { 964, 542, 204, 22, 2196, 11 },
  { 1081, 804, 194, 0, 12818, 20 },
  { 1184, 807, 184, 0, 12818, 20 },
  { 35, 810, 174, 0, 12818, 20 },
  { 168, 813, 164, 0, 12818, 20 },
  { 312, 816, 154, 0, 12818, 20 },
  { 436, 819, 591, 0, 12818, 20 },
  { 555, 822, 2447, 0, 12818, 20 },
  { 677, 825, 1106, 0, 12818, 20 },
  { 128, 16, 1373, 2, 66913, 0 },
  { 260, 16, 1371, 2, 66913, 0 },
  { 384, 16, 1371, 2, 66913, 0 },
  { 506, 16, 1369, 2, 66913, 0 },
  { 632, 16, 1369, 2, 66913, 0 },
  { 750, 16, 1367, 2, 66913, 0 },
  { 864, 16, 1367, 2, 66913, 0 },
  { 970, 16, 1365, 2, 66913, 0 },
  { 1084, 16, 1365, 2, 66913, 0 },
  { 1190, 16, 1363, 2, 66913, 0 },
  { 39, 16, 1363, 2, 66913, 0 },
  { 176, 16, 1361, 2, 66913, 0 },
  { 316, 16, 1359, 2, 66913, 0 },
  { 131, 16, 4021, 2, 65585, 0 },
  { 269, 16, 4012, 2, 65585, 0 },
  { 387, 16, 2490, 2, 65585, 0 },
  { 509, 16, 2478, 2, 65585, 0 },
  { 635, 16, 3974, 2, 65585, 0 },
  { 753, 16, 3956, 2, 65585, 0 },
  { 867, 16, 3863, 2, 65585, 0 },
  { 973, 16, 3844, 2, 65585, 0 },
  { 1087, 16, 3914, 2, 65585, 0 },
  { 1193, 16, 3892, 2, 65585, 0 },
  { 43, 16, 3745, 2, 65585, 0 },
  { 180, 16, 3723, 2, 65585, 0 },
  { 320, 16, 3803, 2, 65585, 0 },
  { 440, 16, 3779, 2, 65585, 0 },
  { 559, 16, 3627, 2, 65585, 0 },
  { 681, 16, 3603, 2, 65585, 0 },
  { 788, 16, 3687, 2, 65585, 0 },
  { 898, 16, 3663, 2, 65585, 0 },
  { 1008, 16, 3507, 2, 65585, 0 },
  { 1118, 16, 3483, 2, 65585, 0 },
  { 79, 16, 3567, 2, 65585, 0 },
  { 212, 16, 3543, 2, 65585, 0 },
  { 356, 16, 3387, 2, 65585, 0 },
  { 472, 16, 3363, 2, 65585, 0 },
  { 595, 16, 3447, 2, 65585, 0 },
  { 713, 16, 3423, 2, 65585, 0 },
  { 824, 16, 3267, 2, 65585, 0 },
  { 930, 16, 3243, 2, 65585, 0 },
  { 1044, 16, 3327, 2, 65585, 0 },
  { 1150, 16, 3303, 2, 65585, 0 },
  { 115, 16, 3172, 2, 65585, 0 },
  { 244, 16, 3148, 2, 65585, 0 },
  { 360, 367, 4015, 29, 5426, 23 },
  { 476, 381, 2502, 29, 5426, 23 },
  { 602, 395, 3992, 29, 5426, 23 },
  { 720, 409, 3882, 29, 5426, 23 },
  { 834, 423, 3936, 29, 5426, 23 },
  { 940, 437, 3767, 29, 5426, 23 },
  { 1054, 451, 3827, 29, 5426, 23 },
  { 1160, 465, 3651, 29, 5426, 23 },
  { 6, 479, 3711, 29, 5426, 23 },
  { 151, 493, 3531, 29, 5426, 23 },
  { 278, 507, 3591, 29, 5426, 23 },
  { 404, 521, 3411, 29, 5426, 23 },
  { 519, 535, 3471, 29, 5426, 23 },
  { 645, 549, 3291, 29, 5426, 23 },
  { 764, 4007, 3351, 11, 17602, 35 },
  { 878, 3948, 3196, 11, 13522, 35 },
  { 984, 1080, 3231, 8, 17329, 39 },
  { 1098, 1080, 3101, 8, 17329, 39 },
  { 55, 1080, 3136, 8, 17329, 39 },
  { 204, 1080, 3031, 8, 17329, 39 },
  { 332, 1080, 3066, 8, 17329, 39 },
  { 452, 1080, 2961, 8, 17329, 39 },
  { 571, 1080, 2996, 8, 17329, 39 },
  { 693, 1080, 2891, 8, 17329, 39 },
  { 800, 1080, 2926, 8, 17329, 39 },
  { 910, 1080, 2820, 8, 17329, 39 },
  { 1020, 1080, 2858, 8, 17329, 39 },
  { 1130, 1080, 2401, 8, 17329, 39 },
  { 91, 1080, 2440, 8, 17329, 39 },
  { 236, 1080, 2791, 8, 17329, 39 },
  { 251, 1339, 1114, 168, 1044, 57 },
  { 375, 1319, 347, 168, 1044, 57 },
  { 497, 1299, 142, 168, 1044, 57 },
  { 626, 1279, 142, 168, 1044, 57 },
  { 741, 1259, 142, 168, 1044, 57 },
  { 858, 1239, 142, 168, 1044, 57 },
  { 961, 1219, 142, 168, 1044, 57 },
  { 1078, 1203, 142, 88, 1456, 74 },
  { 1181, 1191, 142, 76, 2114, 87 },
  { 32, 1179, 142, 76, 2114, 87 },
  { 164, 1167, 142, 76, 2114, 87 },
  { 308, 1155, 142, 76, 2114, 87 },
  { 432, 1143, 142, 76, 2114, 87 },
  { 551, 1131, 344, 76, 2114, 87 },
  { 673, 1119, 1108, 76, 2114, 87 },
  { 491, 2156, 16, 474, 4, 149 },
  { 620, 2101, 16, 474, 4, 149 },
  { 735, 2046, 16, 474, 4, 149 },
  { 852, 1991, 16, 474, 4, 149 },
  { 955, 1936, 16, 474, 4, 149 },
  { 1072, 1885, 16, 423, 272, 166 },
  { 1175, 1838, 16, 376, 512, 181 },
  { 26, 1795, 16, 333, 720, 194 },
  { 158, 1756, 16, 294, 1186, 205 },
  { 301, 1717, 16, 294, 1186, 205 },
  { 424, 1678, 16, 294, 1186, 205 },
  { 543, 1639, 16, 294, 1186, 205 },
  { 665, 1600, 16, 294, 1186, 205 },
  { 1219, 4114, 16, 16, 17856, 2 },
  { 263, 783, 16, 16, 8946, 5 },
  { 503, 786, 16, 16, 8946, 5 },
  { 747, 789, 16, 16, 8946, 5 },
  { 967, 792, 16, 16, 8946, 5 },
  { 1187, 795, 16, 16, 8946, 5 },
  { 172, 798, 16, 16, 8946, 5 },
  { 366, 1513, 1113, 63, 1570, 28 },
  { 482, 4169, 2511, 63, 1570, 28 },
  { 611, 1500, 778, 63, 1570, 28 },
  { 726, 4156, 770, 63, 1570, 28 },
  { 843, 1487, 317, 63, 1570, 28 },
  { 946, 4143, 660, 63, 1570, 28 },
  { 1063, 1474, 308, 63, 1570, 28 },
  { 1166, 4130, 654, 63, 1570, 28 },
  { 16, 1461, 302, 63, 1570, 28 },
  { 134, 4117, 648, 63, 1570, 28 },
  { 289, 1448, 296, 63, 1570, 28 },
  { 412, 4101, 642, 63, 1570, 28 },
  { 531, 1435, 290, 63, 1570, 28 },
  { 653, 4088, 636, 63, 1570, 28 },
  { 776, 1424, 284, 52, 1680, 42 },
  { 886, 4079, 630, 43, 1872, 48 },
  { 996, 1417, 278, 36, 2401, 53 },
  { 1106, 4072, 624, 36, 2401, 53 },
  { 67, 1410, 272, 36, 2401, 53 },
  { 184, 4065, 618, 36, 2401, 53 },
  { 344, 1403, 266, 36, 2401, 53 },
  { 460, 4058, 612, 36, 2401, 53 },
  { 583, 1396, 260, 36, 2401, 53 },
  { 701, 4051, 606, 36, 2401, 53 },
  { 812, 1389, 254, 36, 2401, 53 },
  { 918, 4044, 600, 36, 2401, 53 },
  { 1032, 1382, 765, 36, 2401, 53 },
  { 1138, 4037, 2455, 36, 2401, 53 },
  { 103, 1375, 2474, 36, 2401, 53 },
  { 216, 4030, 1107, 36, 2401, 53 },
  { 599, 1026, 4018, 212, 5314, 92 },
  { 717, 1014, 3953, 212, 5314, 92 },
  { 831, 1002, 4002, 212, 5314, 92 },
  { 937, 990, 3909, 212, 5314, 92 },
  { 1051, 978, 3909, 212, 5314, 92 },
  { 1157, 966, 3798, 212, 5314, 92 },
  { 3, 954, 3798, 212, 5314, 92 },
  { 148, 942, 3682, 212, 5314, 92 },
  { 275, 930, 3682, 212, 5314, 92 },
  { 401, 918, 3562, 212, 5314, 92 },
  { 515, 906, 3562, 212, 5314, 92 },
  { 641, 894, 3442, 212, 5314, 92 },
  { 760, 1070, 3442, 202, 17506, 99 },
  { 874, 1060, 3322, 202, 13426, 99 },
  { 980, 1052, 3322, 194, 14226, 105 },
  { 1094, 1044, 3226, 194, 13698, 105 },
  { 51, 1038, 3226, 188, 14049, 110 },
  { 200, 1038, 3131, 188, 14049, 110 },
  { 328, 1038, 3131, 188, 14049, 110 },
  { 448, 1038, 3061, 188, 14049, 110 },
  { 567, 1038, 3061, 188, 14049, 110 },
  { 689, 1038, 2991, 188, 14049, 110 },
  { 796, 1038, 2991, 188, 14049, 110 },
  { 906, 1038, 2921, 188, 14049, 110 },
  { 1016, 1038, 2921, 188, 14049, 110 },
  { 1126, 1038, 2832, 188, 14049, 110 },
  { 87, 1038, 2855, 188, 14049, 110 },
  { 232, 1038, 2794, 188, 14049, 110 },
  { 828, 2677, 4010, 276, 5170, 114 },
  { 934, 2659, 3951, 276, 5170, 114 },
  { 1048, 2641, 3951, 276, 5170, 114 },
  { 1154, 2623, 3842, 276, 5170, 114 },
  { 0, 2605, 3842, 276, 5170, 114 },
  { 145, 2587, 3743, 276, 5170, 114 },
  { 272, 2569, 3743, 276, 5170, 114 },
  { 398, 2551, 3625, 276, 5170, 114 },
  { 512, 2533, 3625, 276, 5170, 114 },
  { 638, 2515, 3505, 276, 5170, 114 },
  { 756, 2773, 3505, 260, 17378, 123 },
  { 870, 2757, 3385, 260, 13298, 123 },
  { 976, 2743, 3385, 246, 14114, 131 },
  { 1090, 2729, 3265, 246, 13586, 131 },
  { 47, 2717, 3265, 234, 13954, 138 },
  { 196, 2705, 3170, 234, 13778, 138 },
  { 324, 2695, 3170, 224, 13873, 144 },
  { 444, 2695, 3099, 224, 13873, 144 },
  { 563, 2695, 3099, 224, 13873, 144 },
  { 685, 2695, 3029, 224, 13873, 144 },
  { 792, 2695, 3029, 224, 13873, 144 },
  { 902, 2695, 2959, 224, 13873, 144 },
  { 1012, 2695, 2959, 224, 13873, 144 },
  { 1122, 2695, 2856, 224, 13873, 144 },
  { 83, 2695, 2856, 224, 13873, 144 },
  { 228, 2695, 2795, 224, 13873, 144 },
  { 369, 360, 2509, 22, 1956, 11 },
  { 614, 388, 583, 22, 1956, 11 },
  { 846, 416, 756, 22, 1956, 11 },
  { 1066, 444, 747, 22, 1956, 11 },
  { 19, 472, 738, 22, 1956, 11 },
  { 293, 500, 729, 22, 1956, 11 },
  { 535, 528, 720, 22, 1956, 11 },
  { 780, 3839, 711, 3, 2336, 16 },
  { 1000, 562, 702, 0, 8898, 20 },
  { 71, 565, 693, 0, 8898, 20 },
  { 348, 568, 684, 0, 8898, 20 },
  { 587, 571, 675, 0, 8898, 20 },
  { 816, 574, 666, 0, 8898, 20 },
  { 1036, 577, 2460, 0, 8898, 20 },
  { 107, 580, 2468, 0, 8898, 20 },
  { 608, 2343, 2488, 148, 900, 57 },
  { 840, 2323, 588, 148, 900, 57 },
  { 1060, 2303, 588, 148, 900, 57 },
  { 13, 2283, 588, 148, 900, 57 },
  { 286, 2263, 588, 148, 900, 57 },
  { 527, 2243, 588, 148, 900, 57 },
  { 772, 2225, 588, 130, 1328, 66 },
  { 992, 2211, 588, 116, 1776, 81 },
  { 63, 1588, 588, 104, 2034, 87 },
  { 340, 1576, 588, 104, 2034, 87 },
  { 579, 1564, 588, 104, 2034, 87 },
  { 808, 1552, 588, 104, 2034, 87 },
  { 1028, 1540, 588, 104, 2034, 87 },
  { 99, 1528, 2382, 104, 2034, 87 },
};

extern const MCPhysReg ARMRegUnitRoots[][2] = {
  { ARM::APSR },
  { ARM::APSR_NZCV },
  { ARM::CPSR },
  { ARM::FPEXC },
  { ARM::FPINST },
  { ARM::FPSCR, ARM::FPSCR_NZCV },
  { ARM::FPSID },
  { ARM::ITSTATE },
  { ARM::LR },
  { ARM::PC },
  { ARM::SP },
  { ARM::SPSR },
  { ARM::S0 },
  { ARM::S1 },
  { ARM::S2 },
  { ARM::S3 },
  { ARM::S4 },
  { ARM::S5 },
  { ARM::S6 },
  { ARM::S7 },
  { ARM::S8 },
  { ARM::S9 },
  { ARM::S10 },
  { ARM::S11 },
  { ARM::S12 },
  { ARM::S13 },
  { ARM::S14 },
  { ARM::S15 },
  { ARM::S16 },
  { ARM::S17 },
  { ARM::S18 },
  { ARM::S19 },
  { ARM::S20 },
  { ARM::S21 },
  { ARM::S22 },
  { ARM::S23 },
  { ARM::S24 },
  { ARM::S25 },
  { ARM::S26 },
  { ARM::S27 },
  { ARM::S28 },
  { ARM::S29 },
  { ARM::S30 },
  { ARM::S31 },
  { ARM::D16 },
  { ARM::D17 },
  { ARM::D18 },
  { ARM::D19 },
  { ARM::D20 },
  { ARM::D21 },
  { ARM::D22 },
  { ARM::D23 },
  { ARM::D24 },
  { ARM::D25 },
  { ARM::D26 },
  { ARM::D27 },
  { ARM::D28 },
  { ARM::D29 },
  { ARM::D30 },
  { ARM::D31 },
  { ARM::FPINST2 },
  { ARM::MVFR0 },
  { ARM::MVFR1 },
  { ARM::MVFR2 },
  { ARM::R0 },
  { ARM::R1 },
  { ARM::R2 },
  { ARM::R3 },
  { ARM::R4 },
  { ARM::R5 },
  { ARM::R6 },
  { ARM::R7 },
  { ARM::R8 },
  { ARM::R9 },
  { ARM::R10 },
  { ARM::R11 },
  { ARM::R12 },
};

namespace {     // Register classes...
  // HPR Register Class...
  const MCPhysReg HPR[] = {
    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, 
  };

  // HPR Bit set.
  const uint8_t HPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
  };

  // SPR Register Class...
  const MCPhysReg SPR[] = {
    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, 
  };

  // SPR Bit set.
  const uint8_t SPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
  };

  // GPR Register Class...
  const MCPhysReg GPR[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
  };

  // GPR Bit set.
  const uint8_t GPRBits[] = {
    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
  };

  // GPRwithAPSR Register Class...
  const MCPhysReg GPRwithAPSR[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV, 
  };

  // GPRwithAPSR Bit set.
  const uint8_t GPRwithAPSRBits[] = {
    0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
  };

  // SPR_8 Register Class...
  const MCPhysReg SPR_8[] = {
    ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, 
  };

  // SPR_8 Bit set.
  const uint8_t SPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
  };

  // GPRnopc Register Class...
  const MCPhysReg GPRnopc[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 
  };

  // GPRnopc Bit set.
  const uint8_t GPRnopcBits[] = {
    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
  };

  // rGPR Register Class...
  const MCPhysReg rGPR[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 
  };

  // rGPR Bit set.
  const uint8_t rGPRBits[] = {
    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 
  };

  // tGPRwithpc Register Class...
  const MCPhysReg tGPRwithpc[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC, 
  };

  // tGPRwithpc Bit set.
  const uint8_t tGPRwithpcBits[] = {
    0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
  };

  // hGPR Register Class...
  const MCPhysReg hGPR[] = {
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, 
  };

  // hGPR Bit set.
  const uint8_t hGPRBits[] = {
    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
  };

  // tGPR Register Class...
  const MCPhysReg tGPR[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, 
  };

  // tGPR Bit set.
  const uint8_t tGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
  };

  // GPRnopc_and_hGPR Register Class...
  const MCPhysReg GPRnopc_and_hGPR[] = {
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, 
  };

  // GPRnopc_and_hGPR Bit set.
  const uint8_t GPRnopc_and_hGPRBits[] = {
    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
  };

  // hGPR_and_rGPR Register Class...
  const MCPhysReg hGPR_and_rGPR[] = {
    ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 
  };

  // hGPR_and_rGPR Bit set.
  const uint8_t hGPR_and_rGPRBits[] = {
    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 
  };

  // tcGPR Register Class...
  const MCPhysReg tcGPR[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12, 
  };

  // tcGPR Bit set.
  const uint8_t tcGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40, 
  };

  // tGPR_and_tcGPR Register Class...
  const MCPhysReg tGPR_and_tcGPR[] = {
    ARM::R0, ARM::R1, ARM::R2, ARM::R3, 
  };

  // tGPR_and_tcGPR Bit set.
  const uint8_t tGPR_and_tcGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
  };

  // CCR Register Class...
  const MCPhysReg CCR[] = {
    ARM::CPSR, 
  };

  // CCR Bit set.
  const uint8_t CCRBits[] = {
    0x08, 
  };

  // GPRsp Register Class...
  const MCPhysReg GPRsp[] = {
    ARM::SP, 
  };

  // GPRsp Bit set.
  const uint8_t GPRspBits[] = {
    0x00, 0x10, 
  };

  // hGPR_and_tGPRwithpc Register Class...
  const MCPhysReg hGPR_and_tGPRwithpc[] = {
    ARM::PC, 
  };

  // hGPR_and_tGPRwithpc Bit set.
  const uint8_t hGPR_and_tGPRwithpcBits[] = {
    0x00, 0x08, 
  };

  // hGPR_and_tcGPR Register Class...
  const MCPhysReg hGPR_and_tcGPR[] = {
    ARM::R12, 
  };

  // hGPR_and_tcGPR Bit set.
  const uint8_t hGPR_and_tcGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
  };

  // DPR Register Class...
  const MCPhysReg DPR[] = {
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 
  };

  // DPR Bit set.
  const uint8_t DPRBits[] = {
    0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
  };

  // DPR_VFP2 Register Class...
  const MCPhysReg DPR_VFP2[] = {
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, 
  };

  // DPR_VFP2 Bit set.
  const uint8_t DPR_VFP2Bits[] = {
    0x00, 0xc0, 0xff, 0x3f, 
  };

  // DPR_8 Register Class...
  const MCPhysReg DPR_8[] = {
    ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, 
  };

  // DPR_8 Bit set.
  const uint8_t DPR_8Bits[] = {
    0x00, 0xc0, 0x3f, 
  };

  // GPRPair Register Class...
  const MCPhysReg GPRPair[] = {
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 
  };

  // GPRPair Bit set.
  const uint8_t GPRPairBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 
  };

  // GPRPair_with_gsub_1_in_rGPR Register Class...
  const MCPhysReg GPRPair_with_gsub_1_in_rGPR[] = {
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, 
  };

  // GPRPair_with_gsub_1_in_rGPR Bit set.
  const uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 
  };

  // GPRPair_with_gsub_0_in_tGPR Register Class...
  const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
    ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 
  };

  // GPRPair_with_gsub_0_in_tGPR Bit set.
  const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
  };

  // GPRPair_with_gsub_0_in_hGPR Register Class...
  const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
    ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, 
  };

  // GPRPair_with_gsub_0_in_hGPR Bit set.
  const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 
  };

  // GPRPair_with_gsub_0_in_tcGPR Register Class...
  const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
    ARM::R0_R1, ARM::R2_R3, ARM::R12_SP, 
  };

  // GPRPair_with_gsub_0_in_tcGPR Bit set.
  const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 
  };

  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class...
  const MCPhysReg GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = {
    ARM::R8_R9, ARM::R10_R11, 
  };

  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set.
  const uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 
  };

  // GPRPair_with_gsub_1_in_tcGPR Register Class...
  const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = {
    ARM::R0_R1, ARM::R2_R3, 
  };

  // GPRPair_with_gsub_1_in_tcGPR Bit set.
  const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 
  };

  // GPRPair_with_gsub_1_in_GPRsp Register Class...
  const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
    ARM::R12_SP, 
  };

  // GPRPair_with_gsub_1_in_GPRsp Bit set.
  const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
  };

  // DPairSpc Register Class...
  const MCPhysReg DPairSpc[] = {
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D28_D30, ARM::D29_D31, 
  };

  // DPairSpc Bit set.
  const uint8_t DPairSpcBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, 
  };

  // DPairSpc_with_ssub_0 Register Class...
  const MCPhysReg DPairSpc_with_ssub_0[] = {
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 
  };

  // DPairSpc_with_ssub_0 Bit set.
  const uint8_t DPairSpc_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
  };

  // DPairSpc_with_ssub_4 Register Class...
  const MCPhysReg DPairSpc_with_ssub_4[] = {
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, 
  };

  // DPairSpc_with_ssub_4 Bit set.
  const uint8_t DPairSpc_with_ssub_4Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, 
  };

  // DPairSpc_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 
  };

  // DPairSpc_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // DPairSpc_with_dsub_2_in_DPR_8 Register Class...
  const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
    ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, 
  };

  // DPairSpc_with_dsub_2_in_DPR_8 Bit set.
  const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 
  };

  // DPair Register Class...
  const MCPhysReg DPair[] = {
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q15, 
  };

  // DPair Bit set.
  const uint8_t DPairBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
  };

  // DPair_with_ssub_0 Register Class...
  const MCPhysReg DPair_with_ssub_0[] = {
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, 
  };

  // DPair_with_ssub_0 Bit set.
  const uint8_t DPair_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
  };

  // QPR Register Class...
  const MCPhysReg QPR[] = {
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 
  };

  // QPR Bit set.
  const uint8_t QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
  };

  // DPair_with_ssub_2 Register Class...
  const MCPhysReg DPair_with_ssub_2[] = {
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, 
  };

  // DPair_with_ssub_2 Bit set.
  const uint8_t DPair_with_ssub_2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
  };

  // DPair_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, 
  };

  // DPair_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 
  };

  // QPR_VFP2 Register Class...
  const MCPhysReg QPR_VFP2[] = {
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 
  };

  // QPR_VFP2 Bit set.
  const uint8_t QPR_VFP2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
  };

  // DPair_with_dsub_1_in_DPR_8 Register Class...
  const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
    ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, 
  };

  // DPair_with_dsub_1_in_DPR_8 Bit set.
  const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
  };

  // QPR_8 Register Class...
  const MCPhysReg QPR_8[] = {
    ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 
  };

  // QPR_8 Bit set.
  const uint8_t QPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
  };

  // DTriple Register Class...
  const MCPhysReg DTriple[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, ARM::D16_D17_D18, ARM::D17_D18_D19, ARM::D18_D19_D20, ARM::D19_D20_D21, ARM::D20_D21_D22, ARM::D21_D22_D23, ARM::D22_D23_D24, ARM::D23_D24_D25, ARM::D24_D25_D26, ARM::D25_D26_D27, ARM::D26_D27_D28, ARM::D27_D28_D29, ARM::D28_D29_D30, ARM::D29_D30_D31, 
  };

  // DTriple Bit set.
  const uint8_t DTripleBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f, 
  };

  // DTripleSpc Register Class...
  const MCPhysReg DTripleSpc[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 
  };

  // DTripleSpc Bit set.
  const uint8_t DTripleSpcBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 
  };

  // DTripleSpc_with_ssub_0 Register Class...
  const MCPhysReg DTripleSpc_with_ssub_0[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 
  };

  // DTripleSpc_with_ssub_0 Bit set.
  const uint8_t DTripleSpc_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
  };

  // DTriple_with_ssub_0 Register Class...
  const MCPhysReg DTriple_with_ssub_0[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, 
  };

  // DTriple_with_ssub_0 Bit set.
  const uint8_t DTriple_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 
  };

  // DTriple_with_qsub_0_in_QPR Register Class...
  const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, ARM::D16_D17_D18, ARM::D18_D19_D20, ARM::D20_D21_D22, ARM::D22_D23_D24, ARM::D24_D25_D26, ARM::D26_D27_D28, ARM::D28_D29_D30, 
  };

  // DTriple_with_qsub_0_in_QPR Bit set.
  const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15, 
  };

  // DTriple_with_ssub_2 Register Class...
  const MCPhysReg DTriple_with_ssub_2[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, 
  };

  // DTriple_with_ssub_2 Bit set.
  const uint8_t DTriple_with_ssub_2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f, 
  };

  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, ARM::D17_D18_D19, ARM::D19_D20_D21, ARM::D21_D22_D23, ARM::D23_D24_D25, ARM::D25_D26_D27, ARM::D27_D28_D29, ARM::D29_D30_D31, 
  };

  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a, 
  };

  // DTripleSpc_with_ssub_4 Register Class...
  const MCPhysReg DTripleSpc_with_ssub_4[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 
  };

  // DTripleSpc_with_ssub_4 Bit set.
  const uint8_t DTripleSpc_with_ssub_4Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 
  };

  // DTriple_with_ssub_4 Register Class...
  const MCPhysReg DTriple_with_ssub_4[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, 
  };

  // DTriple_with_ssub_4 Bit set.
  const uint8_t DTriple_with_ssub_4Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f, 
  };

  // DTripleSpc_with_ssub_8 Register Class...
  const MCPhysReg DTripleSpc_with_ssub_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 
  };

  // DTripleSpc_with_ssub_8 Bit set.
  const uint8_t DTripleSpc_with_ssub_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 
  };

  // DTripleSpc_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 
  };

  // DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
  };

  // DTriple_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, 
  };

  // DTriple_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 
  };

  // DTriple_with_qsub_0_in_QPR_VFP2 Register Class...
  const MCPhysReg DTriple_with_qsub_0_in_QPR_VFP2[] = {
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, 
  };

  // DTriple_with_qsub_0_in_QPR_VFP2 Bit set.
  const uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 
  };

  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
  const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, 
  };

  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
  const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 
  };

  // DTriple_with_dsub_1_in_DPR_8 Register Class...
  const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, 
  };

  // DTriple_with_dsub_1_in_DPR_8 Bit set.
  const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
  };

  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, 
  };

  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a, 
  };

  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Register Class...
  const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR[] = {
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, 
  };

  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Bit set.
  const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, 
  };

  // DTripleSpc_with_dsub_2_in_DPR_8 Register Class...
  const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 
  };

  // DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
  const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
  };

  // DTriple_with_dsub_2_in_DPR_8 Register Class...
  const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
    ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, 
  };

  // DTriple_with_dsub_2_in_DPR_8 Bit set.
  const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 
  };

  // DTripleSpc_with_dsub_4_in_DPR_8 Register Class...
  const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 
  };

  // DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
  const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
  };

  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
  const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, 
  };

  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
  const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 
  };

  // DTriple_with_qsub_0_in_QPR_8 Register Class...
  const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, 
  };

  // DTriple_with_qsub_0_in_QPR_8 Bit set.
  const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 
  };

  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class...
  const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = {
    ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, 
  };

  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set.
  const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 
  };

  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
  const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
    ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, 
  };

  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
  const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 
  };

  // DQuadSpc Register Class...
  const MCPhysReg DQuadSpc[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, 
  };

  // DQuadSpc Bit set.
  const uint8_t DQuadSpcBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03, 
  };

  // DQuadSpc_with_ssub_0 Register Class...
  const MCPhysReg DQuadSpc_with_ssub_0[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, 
  };

  // DQuadSpc_with_ssub_0 Bit set.
  const uint8_t DQuadSpc_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
  };

  // DQuadSpc_with_ssub_4 Register Class...
  const MCPhysReg DQuadSpc_with_ssub_4[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, 
  };

  // DQuadSpc_with_ssub_4 Bit set.
  const uint8_t DQuadSpc_with_ssub_4Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 
  };

  // DQuadSpc_with_ssub_8 Register Class...
  const MCPhysReg DQuadSpc_with_ssub_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, 
  };

  // DQuadSpc_with_ssub_8 Bit set.
  const uint8_t DQuadSpc_with_ssub_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, 
  };

  // DQuadSpc_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, 
  };

  // DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
  };

  // DQuadSpc_with_dsub_2_in_DPR_8 Register Class...
  const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, 
  };

  // DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
  const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
  };

  // DQuadSpc_with_dsub_4_in_DPR_8 Register Class...
  const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
    ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, 
  };

  // DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
  const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
  };

  // DQuad Register Class...
  const MCPhysReg DQuad[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, ARM::Q8_Q9, ARM::D17_D18_D19_D20, ARM::Q9_Q10, ARM::D19_D20_D21_D22, ARM::Q10_Q11, ARM::D21_D22_D23_D24, ARM::Q11_Q12, ARM::D23_D24_D25_D26, ARM::Q12_Q13, ARM::D25_D26_D27_D28, ARM::Q13_Q14, ARM::D27_D28_D29_D30, ARM::Q14_Q15, 
  };

  // DQuad Bit set.
  const uint8_t DQuadBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
  };

  // DQuad_with_ssub_0 Register Class...
  const MCPhysReg DQuad_with_ssub_0[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, 
  };

  // DQuad_with_ssub_0 Bit set.
  const uint8_t DQuad_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
  };

  // DQuad_with_ssub_2 Register Class...
  const MCPhysReg DQuad_with_ssub_2[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, 
  };

  // DQuad_with_ssub_2 Bit set.
  const uint8_t DQuad_with_ssub_2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
  };

  // QQPR Register Class...
  const MCPhysReg QQPR[] = {
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, 
  };

  // QQPR Bit set.
  const uint8_t QQPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
  };

  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, ARM::D17_D18_D19_D20, ARM::D19_D20_D21_D22, ARM::D21_D22_D23_D24, ARM::D23_D24_D25_D26, ARM::D25_D26_D27_D28, ARM::D27_D28_D29_D30, 
  };

  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
  };

  // DQuad_with_ssub_4 Register Class...
  const MCPhysReg DQuad_with_ssub_4[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, 
  };

  // DQuad_with_ssub_4 Bit set.
  const uint8_t DQuad_with_ssub_4Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
  };

  // DQuad_with_ssub_6 Register Class...
  const MCPhysReg DQuad_with_ssub_6[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, 
  };

  // DQuad_with_ssub_6 Bit set.
  const uint8_t DQuad_with_ssub_6Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 
  };

  // DQuad_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, 
  };

  // DQuad_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
  };

  // DQuad_with_qsub_0_in_QPR_VFP2 Register Class...
  const MCPhysReg DQuad_with_qsub_0_in_QPR_VFP2[] = {
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, 
  };

  // DQuad_with_qsub_0_in_QPR_VFP2 Bit set.
  const uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
  };

  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
  const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, 
  };

  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
  const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
  };

  // DQuad_with_dsub_1_in_DPR_8 Register Class...
  const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, 
  };

  // DQuad_with_dsub_1_in_DPR_8 Bit set.
  const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
  };

  // DQuad_with_qsub_1_in_QPR_VFP2 Register Class...
  const MCPhysReg DQuad_with_qsub_1_in_QPR_VFP2[] = {
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, 
  };

  // DQuad_with_qsub_1_in_QPR_VFP2 Bit set.
  const uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 
  };

  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, 
  };

  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
  };

  // DQuad_with_dsub_2_in_DPR_8 Register Class...
  const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, 
  };

  // DQuad_with_dsub_2_in_DPR_8 Bit set.
  const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
  };

  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
  const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, 
  };

  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
  const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 
  };

  // DQuad_with_dsub_3_in_DPR_8 Register Class...
  const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
    ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, 
  };

  // DQuad_with_dsub_3_in_DPR_8 Bit set.
  const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
  };

  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
  const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, 
  };

  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
  const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
  };

  // DQuad_with_qsub_0_in_QPR_8 Register Class...
  const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = {
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 
  };

  // DQuad_with_qsub_0_in_QPR_8 Bit set.
  const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
  };

  // DQuad_with_qsub_1_in_QPR_8 Register Class...
  const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = {
    ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, 
  };

  // DQuad_with_qsub_1_in_QPR_8 Bit set.
  const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 
  };

  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
  const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, 
  };

  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
  const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
  };

  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
  const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
    ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, 
  };

  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
  const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
  };

  // QQQQPR Register Class...
  const MCPhysReg QQQQPR[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, 
  };

  // QQQQPR Bit set.
  const uint8_t QQQQPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 
  };

  // QQQQPR_with_ssub_0 Register Class...
  const MCPhysReg QQQQPR_with_ssub_0[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, 
  };

  // QQQQPR_with_ssub_0 Bit set.
  const uint8_t QQQQPR_with_ssub_0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
  };

  // QQQQPR_with_ssub_4 Register Class...
  const MCPhysReg QQQQPR_with_ssub_4[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, 
  };

  // QQQQPR_with_ssub_4 Bit set.
  const uint8_t QQQQPR_with_ssub_4Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
  };

  // QQQQPR_with_ssub_8 Register Class...
  const MCPhysReg QQQQPR_with_ssub_8[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, 
  };

  // QQQQPR_with_ssub_8 Bit set.
  const uint8_t QQQQPR_with_ssub_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, 
  };

  // QQQQPR_with_ssub_12 Register Class...
  const MCPhysReg QQQQPR_with_ssub_12[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, 
  };

  // QQQQPR_with_ssub_12 Bit set.
  const uint8_t QQQQPR_with_ssub_12Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01, 
  };

  // QQQQPR_with_dsub_0_in_DPR_8 Register Class...
  const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, 
  };

  // QQQQPR_with_dsub_0_in_DPR_8 Bit set.
  const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 
  };

  // QQQQPR_with_dsub_2_in_DPR_8 Register Class...
  const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 
  };

  // QQQQPR_with_dsub_2_in_DPR_8 Bit set.
  const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
  };

  // QQQQPR_with_dsub_4_in_DPR_8 Register Class...
  const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = {
    ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, 
  };

  // QQQQPR_with_dsub_4_in_DPR_8 Bit set.
  const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
  };

  // QQQQPR_with_dsub_6_in_DPR_8 Register Class...
  const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = {
    ARM::Q0_Q1_Q2_Q3, 
  };

  // QQQQPR_with_dsub_6_in_DPR_8 Bit set.
  const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
  };

} // end anonymous namespace

extern const char ARMRegClassStrings[] = {
  /* 0 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 19 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 40 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 63 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 84 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 102 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 122 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0,
  /* 140 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '1', '2', 0,
  /* 160 */ 'D', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
  /* 169 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
  /* 199 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
  /* 231 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
  /* 261 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
  /* 312 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0,
  /* 365 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
  /* 383 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
  /* 403 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0,
  /* 421 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
  /* 440 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
  /* 461 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
  /* 484 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
  /* 505 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
  /* 523 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0,
  /* 543 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', 0,
  /* 561 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 589 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 619 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 651 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 681 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 708 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 737 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 764 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 791 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 820 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 847 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 875 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 905 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 937 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 967 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 994 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1023 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1050 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1078 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1108 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1140 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '6', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0,
  /* 1168 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
  /* 1195 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
  /* 1224 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
  /* 1251 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
  /* 1299 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0,
  /* 1349 */ 'S', 'P', 'R', '_', '8', 0,
  /* 1355 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
  /* 1374 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
  /* 1395 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0,
  /* 1418 */ 'C', 'C', 'R', 0,
  /* 1422 */ 'D', 'P', 'R', 0,
  /* 1426 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
  /* 1441 */ 't', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0,
  /* 1456 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
  /* 1485 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0,
  /* 1514 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', '_', 'a', 'n', 'd', '_', 'h', 'G', 'P', 'R', 0,
  /* 1531 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', 0,
  /* 1559 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 'r', 'G', 'P', 'R', 0,
  /* 1596 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'r', 'G', 'P', 'R', 0,
  /* 1624 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'G', 'P', 'R', 0,
  /* 1652 */ 'H', 'P', 'R', 0,
  /* 1656 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', 0,
  /* 1663 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 1714 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 1774 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 1842 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 1910 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 1987 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 2064 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 2136 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0,
  /* 2217 */ 'S', 'P', 'R', 0,
  /* 2221 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'A', 'P', 'S', 'R', 0,
  /* 2233 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', 0,
  /* 2242 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', 0,
  /* 2253 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', 0,
  /* 2262 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'w', 'i', 't', 'h', 'p', 'c', 0,
  /* 2282 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', 0,
  /* 2290 */ 'D', 'Q', 'u', 'a', 'd', 0,
  /* 2296 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 0,
  /* 2304 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'G', 'P', 'R', 's', 'p', 0,
  /* 2333 */ 'D', 'P', 'a', 'i', 'r', 0,
  /* 2339 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', 0,
};

extern const MCRegisterClass ARMMCRegisterClasses[] = {
  { HPR, HPRBits, 1652, 32, sizeof(HPRBits), ARM::HPRRegClassID, 1, true },
  { SPR, SPRBits, 2217, 32, sizeof(SPRBits), ARM::SPRRegClassID, 1, true },
  { GPR, GPRBits, 1437, 16, sizeof(GPRBits), ARM::GPRRegClassID, 1, true },
  { GPRwithAPSR, GPRwithAPSRBits, 2221, 16, sizeof(GPRwithAPSRBits), ARM::GPRwithAPSRRegClassID, 1, true },
  { SPR_8, SPR_8Bits, 1349, 16, sizeof(SPR_8Bits), ARM::SPR_8RegClassID, 1, true },
  { GPRnopc, GPRnopcBits, 2282, 15, sizeof(GPRnopcBits), ARM::GPRnopcRegClassID, 1, true },
  { rGPR, rGPRBits, 1591, 14, sizeof(rGPRBits), ARM::rGPRRegClassID, 1, true },
  { tGPRwithpc, tGPRwithpcBits, 2271, 9, sizeof(tGPRwithpcBits), ARM::tGPRwithpcRegClassID, 1, true },
  { hGPR, hGPRBits, 1526, 8, sizeof(hGPRBits), ARM::hGPRRegClassID, 1, true },
  { tGPR, tGPRBits, 1647, 8, sizeof(tGPRBits), ARM::tGPRRegClassID, 1, true },
  { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, 1514, 7, sizeof(GPRnopc_and_hGPRBits), ARM::GPRnopc_and_hGPRRegClassID, 1, true },
  { hGPR_and_rGPR, hGPR_and_rGPRBits, 1582, 6, sizeof(hGPR_and_rGPRBits), ARM::hGPR_and_rGPRRegClassID, 1, true },
  { tcGPR, tcGPRBits, 1435, 5, sizeof(tcGPRBits), ARM::tcGPRRegClassID, 1, true },
  { tGPR_and_tcGPR, tGPR_and_tcGPRBits, 1441, 4, sizeof(tGPR_and_tcGPRBits), ARM::tGPR_and_tcGPRRegClassID, 1, true },
  { CCR, CCRBits, 1418, 1, sizeof(CCRBits), ARM::CCRRegClassID, -1, false },
  { GPRsp, GPRspBits, 2327, 1, sizeof(GPRspBits), ARM::GPRspRegClassID, 1, true },
  { hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, 2262, 1, sizeof(hGPR_and_tGPRwithpcBits), ARM::hGPR_and_tGPRwithpcRegClassID, 1, true },
  { hGPR_and_tcGPR, hGPR_and_tcGPRBits, 1426, 1, sizeof(hGPR_and_tcGPRBits), ARM::hGPR_and_tcGPRRegClassID, 1, true },
  { DPR, DPRBits, 1422, 32, sizeof(DPRBits), ARM::DPRRegClassID, 1, true },
  { DPR_VFP2, DPR_VFP2Bits, 160, 16, sizeof(DPR_VFP2Bits), ARM::DPR_VFP2RegClassID, 1, true },
  { DPR_8, DPR_8Bits, 583, 8, sizeof(DPR_8Bits), ARM::DPR_8RegClassID, 1, true },
  { GPRPair, GPRPairBits, 2339, 7, sizeof(GPRPairBits), ARM::GPRPairRegClassID, 1, true },
  { GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, 1596, 6, sizeof(GPRPair_with_gsub_1_in_rGPRBits), ARM::GPRPair_with_gsub_1_in_rGPRRegClassID, 1, true },
  { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, 1624, 4, sizeof(GPRPair_with_gsub_0_in_tGPRBits), ARM::GPRPair_with_gsub_0_in_tGPRRegClassID, 1, true },
  { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, 1531, 3, sizeof(GPRPair_with_gsub_0_in_hGPRBits), ARM::GPRPair_with_gsub_0_in_hGPRRegClassID, 1, true },
  { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, 1456, 3, sizeof(GPRPair_with_gsub_0_in_tcGPRBits), ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID, 1, true },
  { GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, 1559, 2, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits), ARM::GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID, 1, true },
  { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, 1485, 2, sizeof(GPRPair_with_gsub_1_in_tcGPRBits), ARM::GPRPair_with_gsub_1_in_tcGPRRegClassID, 1, true },
  { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, 2304, 1, sizeof(GPRPair_with_gsub_1_in_GPRspBits), ARM::GPRPair_with_gsub_1_in_GPRspRegClassID, 1, true },
  { DPairSpc, DPairSpcBits, 2253, 30, sizeof(DPairSpcBits), ARM::DPairSpcRegClassID, 1, true },
  { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, 63, 16, sizeof(DPairSpc_with_ssub_0Bits), ARM::DPairSpc_with_ssub_0RegClassID, 1, true },
  { DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, 484, 14, sizeof(DPairSpc_with_ssub_4Bits), ARM::DPairSpc_with_ssub_4RegClassID, 1, true },
  { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, 651, 8, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID, 1, true },
  { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, 937, 6, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), ARM::DPairSpc_with_dsub_2_in_DPR_8RegClassID, 1, true },
  { DPair, DPairBits, 2333, 31, sizeof(DPairBits), ARM::DPairRegClassID, 1, true },
  { DPair_with_ssub_0, DPair_with_ssub_0Bits, 122, 16, sizeof(DPair_with_ssub_0Bits), ARM::DPair_with_ssub_0RegClassID, 1, true },
  { QPR, QPRBits, 1659, 16, sizeof(QPRBits), ARM::QPRRegClassID, 1, true },
  { DPair_with_ssub_2, DPair_with_ssub_2Bits, 403, 15, sizeof(DPair_with_ssub_2Bits), ARM::DPair_with_ssub_2RegClassID, 1, true },
  { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, 737, 8, sizeof(DPair_with_dsub_0_in_DPR_8Bits), ARM::DPair_with_dsub_0_in_DPR_8RegClassID, 1, true },
  { QPR_VFP2, QPR_VFP2Bits, 190, 8, sizeof(QPR_VFP2Bits), ARM::QPR_VFP2RegClassID, 1, true },
  { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, 820, 7, sizeof(DPair_with_dsub_1_in_DPR_8Bits), ARM::DPair_with_dsub_1_in_DPR_8RegClassID, 1, true },
  { QPR_8, QPR_8Bits, 1189, 4, sizeof(QPR_8Bits), ARM::QPR_8RegClassID, 1, true },
  { DTriple, DTripleBits, 2296, 30, sizeof(DTripleBits), ARM::DTripleRegClassID, 1, true },
  { DTripleSpc, DTripleSpcBits, 2242, 28, sizeof(DTripleSpcBits), ARM::DTripleSpcRegClassID, 1, true },
  { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, 40, 16, sizeof(DTripleSpc_with_ssub_0Bits), ARM::DTripleSpc_with_ssub_0RegClassID, 1, true },
  { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, 102, 16, sizeof(DTriple_with_ssub_0Bits), ARM::DTriple_with_ssub_0RegClassID, 1, true },
  { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, 1687, 15, sizeof(DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_qsub_0_in_QPRRegClassID, 1, true },
  { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, 383, 15, sizeof(DTriple_with_ssub_2Bits), ARM::DTriple_with_ssub_2RegClassID, 1, true },
  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2088, 15, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
  { DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, 461, 14, sizeof(DTripleSpc_with_ssub_4Bits), ARM::DTripleSpc_with_ssub_4RegClassID, 1, true },
  { DTriple_with_ssub_4, DTriple_with_ssub_4Bits, 523, 14, sizeof(DTriple_with_ssub_4Bits), ARM::DTriple_with_ssub_4RegClassID, 1, true },
  { DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, 1395, 12, sizeof(DTripleSpc_with_ssub_8Bits), ARM::DTripleSpc_with_ssub_8RegClassID, 1, true },
  { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, 619, 8, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, 1, true },
  { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, 708, 8, sizeof(DTriple_with_dsub_0_in_DPR_8Bits), ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, 1, true },
  { DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, 199, 8, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits), ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClassID, 1, true },
  { DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2064, 8, sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
  { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, 791, 7, sizeof(DTriple_with_dsub_1_in_DPR_8Bits), ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, 1, true },
  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, 312, 7, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID, 1, true },
  { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits, 1663, 7, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID, 1, true },
  { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, 905, 6, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, 1, true },
  { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, 994, 6, sizeof(DTriple_with_dsub_2_in_DPR_8Bits), ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, 1, true },
  { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, 1108, 4, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID, 1, true },
  { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2136, 4, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
  { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, 1195, 4, sizeof(DTriple_with_qsub_0_in_QPR_8Bits), ARM::DTriple_with_qsub_0_in_QPR_8RegClassID, 1, true },
  { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, 1714, 3, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID, 1, true },
  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1299, 3, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 1, true },
  { DQuadSpc, DQuadSpcBits, 2233, 28, sizeof(DQuadSpcBits), ARM::DQuadSpcRegClassID, 1, true },
  { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, 19, 16, sizeof(DQuadSpc_with_ssub_0Bits), ARM::DQuadSpc_with_ssub_0RegClassID, 1, true },
  { DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, 440, 14, sizeof(DQuadSpc_with_ssub_4Bits), ARM::DQuadSpc_with_ssub_4RegClassID, 1, true },
  { DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, 1374, 12, sizeof(DQuadSpc_with_ssub_8Bits), ARM::DQuadSpc_with_ssub_8RegClassID, 1, true },
  { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, 589, 8, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID, 1, true },
  { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, 875, 6, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID, 1, true },
  { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, 1078, 4, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID, 1, true },
  { DQuad, DQuadBits, 2290, 29, sizeof(DQuadBits), ARM::DQuadRegClassID, 1, true },
  { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, 84, 16, sizeof(DQuad_with_ssub_0Bits), ARM::DQuad_with_ssub_0RegClassID, 1, true },
  { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, 365, 15, sizeof(DQuad_with_ssub_2Bits), ARM::DQuad_with_ssub_2RegClassID, 1, true },
  { QQPR, QQPRBits, 1658, 15, sizeof(QQPRBits), ARM::QQPRRegClassID, 1, true },
  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1796, 14, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
  { DQuad_with_ssub_4, DQuad_with_ssub_4Bits, 505, 14, sizeof(DQuad_with_ssub_4Bits), ARM::DQuad_with_ssub_4RegClassID, 1, true },
  { DQuad_with_ssub_6, DQuad_with_ssub_6Bits, 543, 13, sizeof(DQuad_with_ssub_6Bits), ARM::DQuad_with_ssub_6RegClassID, 1, true },
  { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, 681, 8, sizeof(DQuad_with_dsub_0_in_DPR_8Bits), ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, 1, true },
  { DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, 169, 8, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClassID, 1, true },
  { DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1774, 8, sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
  { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, 764, 7, sizeof(DQuad_with_dsub_1_in_DPR_8Bits), ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, 1, true },
  { DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, 231, 7, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits), ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID, 1, true },
  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, 261, 7, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID, 1, true },
  { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, 967, 6, sizeof(DQuad_with_dsub_2_in_DPR_8Bits), ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, 1, true },
  { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1842, 6, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
  { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, 1023, 5, sizeof(DQuad_with_dsub_3_in_DPR_8Bits), ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, 1, true },
  { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1910, 4, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
  { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, 1168, 4, sizeof(DQuad_with_qsub_0_in_QPR_8Bits), ARM::DQuad_with_qsub_0_in_QPR_8RegClassID, 1, true },
  { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, 1224, 3, sizeof(DQuad_with_qsub_1_in_QPR_8Bits), ARM::DQuad_with_qsub_1_in_QPR_8RegClassID, 1, true },
  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1251, 3, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 1, true },
  { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 1987, 2, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true },
  { QQQQPR, QQQQPRBits, 1656, 13, sizeof(QQQQPRBits), ARM::QQQQPRRegClassID, 1, true },
  { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, 0, 8, sizeof(QQQQPR_with_ssub_0Bits), ARM::QQQQPR_with_ssub_0RegClassID, 1, true },
  { QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, 421, 7, sizeof(QQQQPR_with_ssub_4Bits), ARM::QQQQPR_with_ssub_4RegClassID, 1, true },
  { QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, 1355, 6, sizeof(QQQQPR_with_ssub_8Bits), ARM::QQQQPR_with_ssub_8RegClassID, 1, true },
  { QQQQPR_with_ssub_12, QQQQPR_with_ssub_12Bits, 140, 5, sizeof(QQQQPR_with_ssub_12Bits), ARM::QQQQPR_with_ssub_12RegClassID, 1, true },
  { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, 561, 4, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits), ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID, 1, true },
  { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, 847, 3, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits), ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID, 1, true },
  { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, 1050, 2, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits), ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID, 1, true },
  { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, 1140, 1, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits), ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID, 1, true },
};

// ARM Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = {
  { 0U, ARM::R0 },
  { 1U, ARM::R1 },
  { 2U, ARM::R2 },
  { 3U, ARM::R3 },
  { 4U, ARM::R4 },
  { 5U, ARM::R5 },
  { 6U, ARM::R6 },
  { 7U, ARM::R7 },
  { 8U, ARM::R8 },
  { 9U, ARM::R9 },
  { 10U, ARM::R10 },
  { 11U, ARM::R11 },
  { 12U, ARM::R12 },
  { 13U, ARM::SP },
  { 14U, ARM::LR },
  { 15U, ARM::PC },
  { 256U, ARM::D0 },
  { 257U, ARM::D1 },
  { 258U, ARM::D2 },
  { 259U, ARM::D3 },
  { 260U, ARM::D4 },
  { 261U, ARM::D5 },
  { 262U, ARM::D6 },
  { 263U, ARM::D7 },
  { 264U, ARM::D8 },
  { 265U, ARM::D9 },
  { 266U, ARM::D10 },
  { 267U, ARM::D11 },
  { 268U, ARM::D12 },
  { 269U, ARM::D13 },
  { 270U, ARM::D14 },
  { 271U, ARM::D15 },
  { 272U, ARM::D16 },
  { 273U, ARM::D17 },
  { 274U, ARM::D18 },
  { 275U, ARM::D19 },
  { 276U, ARM::D20 },
  { 277U, ARM::D21 },
  { 278U, ARM::D22 },
  { 279U, ARM::D23 },
  { 280U, ARM::D24 },
  { 281U, ARM::D25 },
  { 282U, ARM::D26 },
  { 283U, ARM::D27 },
  { 284U, ARM::D28 },
  { 285U, ARM::D29 },
  { 286U, ARM::D30 },
  { 287U, ARM::D31 },
};
extern const unsigned ARMDwarfFlavour0Dwarf2LSize = array_lengthof(ARMDwarfFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = {
  { 0U, ARM::R0 },
  { 1U, ARM::R1 },
  { 2U, ARM::R2 },
  { 3U, ARM::R3 },
  { 4U, ARM::R4 },
  { 5U, ARM::R5 },
  { 6U, ARM::R6 },
  { 7U, ARM::R7 },
  { 8U, ARM::R8 },
  { 9U, ARM::R9 },
  { 10U, ARM::R10 },
  { 11U, ARM::R11 },
  { 12U, ARM::R12 },
  { 13U, ARM::SP },
  { 14U, ARM::LR },
  { 15U, ARM::PC },
  { 256U, ARM::D0 },
  { 257U, ARM::D1 },
  { 258U, ARM::D2 },
  { 259U, ARM::D3 },
  { 260U, ARM::D4 },
  { 261U, ARM::D5 },
  { 262U, ARM::D6 },
  { 263U, ARM::D7 },
  { 264U, ARM::D8 },
  { 265U, ARM::D9 },
  { 266U, ARM::D10 },
  { 267U, ARM::D11 },
  { 268U, ARM::D12 },
  { 269U, ARM::D13 },
  { 270U, ARM::D14 },
  { 271U, ARM::D15 },
  { 272U, ARM::D16 },
  { 273U, ARM::D17 },
  { 274U, ARM::D18 },
  { 275U, ARM::D19 },
  { 276U, ARM::D20 },
  { 277U, ARM::D21 },
  { 278U, ARM::D22 },
  { 279U, ARM::D23 },
  { 280U, ARM::D24 },
  { 281U, ARM::D25 },
  { 282U, ARM::D26 },
  { 283U, ARM::D27 },
  { 284U, ARM::D28 },
  { 285U, ARM::D29 },
  { 286U, ARM::D30 },
  { 287U, ARM::D31 },
};
extern const unsigned ARMEHFlavour0Dwarf2LSize = array_lengthof(ARMEHFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = {
  { ARM::LR, 14U },
  { ARM::PC, 15U },
  { ARM::SP, 13U },
  { ARM::D0, 256U },
  { ARM::D1, 257U },
  { ARM::D2, 258U },
  { ARM::D3, 259U },
  { ARM::D4, 260U },
  { ARM::D5, 261U },
  { ARM::D6, 262U },
  { ARM::D7, 263U },
  { ARM::D8, 264U },
  { ARM::D9, 265U },
  { ARM::D10, 266U },
  { ARM::D11, 267U },
  { ARM::D12, 268U },
  { ARM::D13, 269U },
  { ARM::D14, 270U },
  { ARM::D15, 271U },
  { ARM::D16, 272U },
  { ARM::D17, 273U },
  { ARM::D18, 274U },
  { ARM::D19, 275U },
  { ARM::D20, 276U },
  { ARM::D21, 277U },
  { ARM::D22, 278U },
  { ARM::D23, 279U },
  { ARM::D24, 280U },
  { ARM::D25, 281U },
  { ARM::D26, 282U },
  { ARM::D27, 283U },
  { ARM::D28, 284U },
  { ARM::D29, 285U },
  { ARM::D30, 286U },
  { ARM::D31, 287U },
  { ARM::R0, 0U },
  { ARM::R1, 1U },
  { ARM::R2, 2U },
  { ARM::R3, 3U },
  { ARM::R4, 4U },
  { ARM::R5, 5U },
  { ARM::R6, 6U },
  { ARM::R7, 7U },
  { ARM::R8, 8U },
  { ARM::R9, 9U },
  { ARM::R10, 10U },
  { ARM::R11, 11U },
  { ARM::R12, 12U },
};
extern const unsigned ARMDwarfFlavour0L2DwarfSize = array_lengthof(ARMDwarfFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = {
  { ARM::LR, 14U },
  { ARM::PC, 15U },
  { ARM::SP, 13U },
  { ARM::D0, 256U },
  { ARM::D1, 257U },
  { ARM::D2, 258U },
  { ARM::D3, 259U },
  { ARM::D4, 260U },
  { ARM::D5, 261U },
  { ARM::D6, 262U },
  { ARM::D7, 263U },
  { ARM::D8, 264U },
  { ARM::D9, 265U },
  { ARM::D10, 266U },
  { ARM::D11, 267U },
  { ARM::D12, 268U },
  { ARM::D13, 269U },
  { ARM::D14, 270U },
  { ARM::D15, 271U },
  { ARM::D16, 272U },
  { ARM::D17, 273U },
  { ARM::D18, 274U },
  { ARM::D19, 275U },
  { ARM::D20, 276U },
  { ARM::D21, 277U },
  { ARM::D22, 278U },
  { ARM::D23, 279U },
  { ARM::D24, 280U },
  { ARM::D25, 281U },
  { ARM::D26, 282U },
  { ARM::D27, 283U },
  { ARM::D28, 284U },
  { ARM::D29, 285U },
  { ARM::D30, 286U },
  { ARM::D31, 287U },
  { ARM::R0, 0U },
  { ARM::R1, 1U },
  { ARM::R2, 2U },
  { ARM::R3, 3U },
  { ARM::R4, 4U },
  { ARM::R5, 5U },
  { ARM::R6, 6U },
  { ARM::R7, 7U },
  { ARM::R8, 8U },
  { ARM::R9, 9U },
  { ARM::R10, 10U },
  { ARM::R11, 11U },
  { ARM::R12, 12U },
};
extern const unsigned ARMEHFlavour0L2DwarfSize = array_lengthof(ARMEHFlavour0L2Dwarf);

extern const uint16_t ARMRegEncodingTable[] = {
  0,
  1,
  15,
  0,
  8,
  9,
  3,
  3,
  0,
  4,
  14,
  15,
  13,
  2,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  10,
  7,
  6,
  5,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  12,
  0,
  2,
  4,
  6,
  8,
  10,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  1,
  3,
  5,
  7,
  9,
  11,
  13,
  15,
  17,
  19,
  21,
  23,
  25,
  27,
  29,
  1,
  3,
  5,
  7,
  9,
  11,
  13,
  15,
  17,
  19,
  21,
  23,
  25,
  27,
};
static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(ARMRegDesc, 289, RA, PC, ARMMCRegisterClasses, 103, ARMRegUnitRoots, 77, ARMRegDiffLists, ARMLaneMaskLists, ARMRegStrings, ARMRegClassStrings, ARMSubRegIdxLists, 57,
ARMSubRegIdxRanges, ARMRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true);
    break;
  }
}

} // end namespace llvm

#endif // GET_REGINFO_MC_DESC

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Register Information Header Fragment                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER

#include "llvm/CodeGen/TargetRegisterInfo.h"

namespace llvm {

class ARMFrameLowering;

struct ARMGenRegisterInfo : public TargetRegisterInfo {
  explicit ARMGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
      unsigned PC = 0, unsigned HwMode = 0);
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
  unsigned getNumRegPressureSets() const override;
  const char *getRegPressureSetName(unsigned Idx) const override;
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
  ArrayRef<const char *> getRegMaskNames() const override;
  ArrayRef<const uint32_t *> getRegMasks() const override;
  /// Devirtualized TargetFrameLowering.
  static const ARMFrameLowering *getFrameLowering(
      const MachineFunction &MF);
};

namespace ARM { // Register classes
  extern const TargetRegisterClass HPRRegClass;
  extern const TargetRegisterClass SPRRegClass;
  extern const TargetRegisterClass GPRRegClass;
  extern const TargetRegisterClass GPRwithAPSRRegClass;
  extern const TargetRegisterClass SPR_8RegClass;
  extern const TargetRegisterClass GPRnopcRegClass;
  extern const TargetRegisterClass rGPRRegClass;
  extern const TargetRegisterClass tGPRwithpcRegClass;
  extern const TargetRegisterClass hGPRRegClass;
  extern const TargetRegisterClass tGPRRegClass;
  extern const TargetRegisterClass GPRnopc_and_hGPRRegClass;
  extern const TargetRegisterClass hGPR_and_rGPRRegClass;
  extern const TargetRegisterClass tcGPRRegClass;
  extern const TargetRegisterClass tGPR_and_tcGPRRegClass;
  extern const TargetRegisterClass CCRRegClass;
  extern const TargetRegisterClass GPRspRegClass;
  extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass;
  extern const TargetRegisterClass hGPR_and_tcGPRRegClass;
  extern const TargetRegisterClass DPRRegClass;
  extern const TargetRegisterClass DPR_VFP2RegClass;
  extern const TargetRegisterClass DPR_8RegClass;
  extern const TargetRegisterClass GPRPairRegClass;
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_rGPRRegClass;
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass;
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass;
  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass;
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass;
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass;
  extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass;
  extern const TargetRegisterClass DPairSpcRegClass;
  extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass;
  extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass;
  extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass;
  extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass;
  extern const TargetRegisterClass DPairRegClass;
  extern const TargetRegisterClass DPair_with_ssub_0RegClass;
  extern const TargetRegisterClass QPRRegClass;
  extern const TargetRegisterClass DPair_with_ssub_2RegClass;
  extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass;
  extern const TargetRegisterClass QPR_VFP2RegClass;
  extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass;
  extern const TargetRegisterClass QPR_8RegClass;
  extern const TargetRegisterClass DTripleRegClass;
  extern const TargetRegisterClass DTripleSpcRegClass;
  extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass;
  extern const TargetRegisterClass DTriple_with_ssub_0RegClass;
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass;
  extern const TargetRegisterClass DTriple_with_ssub_2RegClass;
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
  extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass;
  extern const TargetRegisterClass DTriple_with_ssub_4RegClass;
  extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass;
  extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass;
  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass;
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_VFP2RegClass;
  extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
  extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass;
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass;
  extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass;
  extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass;
  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass;
  extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass;
  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass;
  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass;
  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
  extern const TargetRegisterClass DQuadSpcRegClass;
  extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass;
  extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass;
  extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass;
  extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass;
  extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass;
  extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass;
  extern const TargetRegisterClass DQuadRegClass;
  extern const TargetRegisterClass DQuad_with_ssub_0RegClass;
  extern const TargetRegisterClass DQuad_with_ssub_2RegClass;
  extern const TargetRegisterClass QQPRRegClass;
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
  extern const TargetRegisterClass DQuad_with_ssub_4RegClass;
  extern const TargetRegisterClass DQuad_with_ssub_6RegClass;
  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass;
  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_VFP2RegClass;
  extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
  extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass;
  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_VFP2RegClass;
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass;
  extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass;
  extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass;
  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass;
  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass;
  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
  extern const TargetRegisterClass QQQQPRRegClass;
  extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass;
  extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass;
  extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass;
  extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass;
  extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass;
  extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass;
  extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass;
  extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass;
} // end namespace ARM

} // end namespace llvm

#endif // GET_REGINFO_HEADER

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC

namespace llvm {

extern const MCRegisterClass ARMMCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::i32, MVT::Other,
  /* 2 */ MVT::f16, MVT::Other,
  /* 4 */ MVT::f32, MVT::Other,
  /* 6 */ MVT::v2i64, MVT::Other,
  /* 8 */ MVT::v4i64, MVT::Other,
  /* 10 */ MVT::v8i64, MVT::Other,
  /* 12 */ MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v2f32, MVT::v4f16, MVT::Other,
  /* 20 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other,
  /* 28 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other,
  /* 35 */ MVT::Untyped, MVT::Other,
};

static const char *const SubRegIndexNameTable[] = { "dsub_0", "dsub_1", "dsub_2", "dsub_3", "dsub_4", "dsub_5", "dsub_6", "dsub_7", "gsub_0", "gsub_1", "qqsub_0", "qqsub_1", "qsub_0", "qsub_1", "qsub_2", "qsub_3", "ssub_0", "ssub_1", "ssub_2", "ssub_3", "ssub_4", "ssub_5", "ssub_6", "ssub_7", "ssub_8", "ssub_9", "ssub_10", "ssub_11", "ssub_12", "ssub_13", "dsub_7_then_ssub_0", "dsub_7_then_ssub_1", "ssub_0_ssub_1_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5", "ssub_2_ssub_3_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_6_ssub_7_dsub_5", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5", "ssub_6_ssub_7_dsub_5_dsub_7", "ssub_6_ssub_7_ssub_8_ssub_9", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "ssub_8_ssub_9_ssub_12_ssub_13", "ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "dsub_5_dsub_7", "dsub_5_ssub_12_ssub_13_dsub_7", "dsub_5_ssub_12_ssub_13", "ssub_4_ssub_5_ssub_6_ssub_7_qsub_2", "" };


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
  LaneBitmask(0x0000000C), // dsub_0
  LaneBitmask(0x00000030), // dsub_1
  LaneBitmask(0x000000C0), // dsub_2
  LaneBitmask(0x00000300), // dsub_3
  LaneBitmask(0x00000C00), // dsub_4
  LaneBitmask(0x00003000), // dsub_5
  LaneBitmask(0x0000C000), // dsub_6
  LaneBitmask(0x00030000), // dsub_7
  LaneBitmask(0x00000001), // gsub_0
  LaneBitmask(0x00000002), // gsub_1
  LaneBitmask(0x000003FC), // qqsub_0
  LaneBitmask(0x0003FC00), // qqsub_1
  LaneBitmask(0x0000003C), // qsub_0
  LaneBitmask(0x000003C0), // qsub_1
  LaneBitmask(0x00003C00), // qsub_2
  LaneBitmask(0x0003C000), // qsub_3
  LaneBitmask(0x00000004), // ssub_0
  LaneBitmask(0x00000008), // ssub_1
  LaneBitmask(0x00000010), // ssub_2
  LaneBitmask(0x00000020), // ssub_3
  LaneBitmask(0x00000040), // ssub_4
  LaneBitmask(0x00000080), // ssub_5
  LaneBitmask(0x00000100), // ssub_6
  LaneBitmask(0x00000200), // ssub_7
  LaneBitmask(0x00000400), // ssub_8
  LaneBitmask(0x00000800), // ssub_9
  LaneBitmask(0x00001000), // ssub_10
  LaneBitmask(0x00002000), // ssub_11
  LaneBitmask(0x00004000), // ssub_12
  LaneBitmask(0x00008000), // ssub_13
  LaneBitmask(0x00010000), // dsub_7_then_ssub_0
  LaneBitmask(0x00020000), // dsub_7_then_ssub_1
  LaneBitmask(0x000000CC), // ssub_0_ssub_1_ssub_4_ssub_5
  LaneBitmask(0x000000FC), // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  LaneBitmask(0x00000330), // ssub_2_ssub_3_ssub_6_ssub_7
  LaneBitmask(0x000003F0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  LaneBitmask(0x000000F0), // ssub_2_ssub_3_ssub_4_ssub_5
  LaneBitmask(0x00000CCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  LaneBitmask(0x0000CCCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  LaneBitmask(0x00003330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  LaneBitmask(0x00033330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
  LaneBitmask(0x00000FF0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  LaneBitmask(0x00000CC0), // ssub_4_ssub_5_ssub_8_ssub_9
  LaneBitmask(0x00000FC0), // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  LaneBitmask(0x0000CCC0), // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  LaneBitmask(0x00003300), // ssub_6_ssub_7_dsub_5
  LaneBitmask(0x00003F00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  LaneBitmask(0x00033300), // ssub_6_ssub_7_dsub_5_dsub_7
  LaneBitmask(0x00000F00), // ssub_6_ssub_7_ssub_8_ssub_9
  LaneBitmask(0x0000FF00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  LaneBitmask(0x0000CC00), // ssub_8_ssub_9_ssub_12_ssub_13
  LaneBitmask(0x0000FC00), // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  LaneBitmask(0x00033000), // dsub_5_dsub_7
  LaneBitmask(0x0003F000), // dsub_5_ssub_12_ssub_13_dsub_7
  LaneBitmask(0x0000F000), // dsub_5_ssub_12_ssub_13
  LaneBitmask(0x00003FC0), // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
 };



static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 16, 16, 32, VTLists+2 },    // HPR
  { 32, 32, 32, VTLists+4 },    // SPR
  { 32, 32, 32, VTLists+0 },    // GPR
  { 32, 32, 32, VTLists+0 },    // GPRwithAPSR
  { 32, 32, 32, VTLists+4 },    // SPR_8
  { 32, 32, 32, VTLists+0 },    // GPRnopc
  { 32, 32, 32, VTLists+0 },    // rGPR
  { 32, 32, 32, VTLists+0 },    // tGPRwithpc
  { 32, 32, 32, VTLists+0 },    // hGPR
  { 32, 32, 32, VTLists+0 },    // tGPR
  { 32, 32, 32, VTLists+0 },    // GPRnopc_and_hGPR
  { 32, 32, 32, VTLists+0 },    // hGPR_and_rGPR
  { 32, 32, 32, VTLists+0 },    // tcGPR
  { 32, 32, 32, VTLists+0 },    // tGPR_and_tcGPR
  { 32, 32, 32, VTLists+0 },    // CCR
  { 32, 32, 32, VTLists+0 },    // GPRsp
  { 32, 32, 32, VTLists+0 },    // hGPR_and_tGPRwithpc
  { 32, 32, 32, VTLists+0 },    // hGPR_and_tcGPR
  { 64, 64, 64, VTLists+12 },    // DPR
  { 64, 64, 64, VTLists+12 },    // DPR_VFP2
  { 64, 64, 64, VTLists+12 },    // DPR_8
  { 64, 64, 64, VTLists+35 },    // GPRPair
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_rGPR
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_0_in_tGPR
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_0_in_hGPR
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_0_in_tcGPR
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_hGPR_and_rGPR
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_tcGPR
  { 64, 64, 64, VTLists+35 },    // GPRPair_with_gsub_1_in_GPRsp
  { 128, 128, 64, VTLists+6 },    // DPairSpc
  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_ssub_0
  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_ssub_4
  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_dsub_0_in_DPR_8
  { 128, 128, 64, VTLists+6 },    // DPairSpc_with_dsub_2_in_DPR_8
  { 128, 128, 128, VTLists+28 },    // DPair
  { 128, 128, 128, VTLists+28 },    // DPair_with_ssub_0
  { 128, 128, 128, VTLists+20 },    // QPR
  { 128, 128, 128, VTLists+28 },    // DPair_with_ssub_2
  { 128, 128, 128, VTLists+28 },    // DPair_with_dsub_0_in_DPR_8
  { 128, 128, 128, VTLists+28 },    // QPR_VFP2
  { 128, 128, 128, VTLists+28 },    // DPair_with_dsub_1_in_DPR_8
  { 128, 128, 128, VTLists+28 },    // QPR_8
  { 192, 192, 64, VTLists+35 },    // DTriple
  { 192, 192, 64, VTLists+35 },    // DTripleSpc
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_ssub_0
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_0
  { 192, 192, 64, VTLists+35 },    // DTriple_with_qsub_0_in_QPR
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_ssub_4
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_4
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_ssub_8
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_dsub_0_in_DPR_8
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_0_in_DPR_8
  { 192, 192, 64, VTLists+35 },    // DTriple_with_qsub_0_in_QPR_VFP2
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_1_in_DPR_8
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_dsub_2_in_DPR_8
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_2_in_DPR_8
  { 192, 192, 64, VTLists+35 },    // DTripleSpc_with_dsub_4_in_DPR_8
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
  { 192, 192, 64, VTLists+35 },    // DTriple_with_qsub_0_in_QPR_8
  { 192, 192, 64, VTLists+35 },    // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
  { 192, 192, 64, VTLists+35 },    // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
  { 256, 256, 64, VTLists+8 },    // DQuadSpc
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_ssub_0
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_ssub_4
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_ssub_8
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_dsub_0_in_DPR_8
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_dsub_2_in_DPR_8
  { 256, 256, 64, VTLists+8 },    // DQuadSpc_with_dsub_4_in_DPR_8
  { 256, 256, 256, VTLists+8 },    // DQuad
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_0
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2
  { 256, 256, 256, VTLists+8 },    // QQPR
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_4
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_6
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_0_in_DPR_8
  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_0_in_QPR_VFP2
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_1_in_DPR_8
  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_1_in_QPR_VFP2
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_2_in_DPR_8
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_3_in_DPR_8
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_0_in_QPR_8
  { 256, 256, 256, VTLists+8 },    // DQuad_with_qsub_1_in_QPR_8
  { 256, 256, 256, VTLists+8 },    // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
  { 256, 256, 256, VTLists+8 },    // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
  { 512, 512, 256, VTLists+10 },    // QQQQPR
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_0
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_4
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_8
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_ssub_12
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_0_in_DPR_8
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_2_in_DPR_8
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_4_in_DPR_8
  { 512, 512, 256, VTLists+10 },    // QQQQPR_with_dsub_6_in_DPR_8
};

static const TargetRegisterClass *const NullRegClasses[] = { nullptr };

static const uint32_t HPRSubClassMask[] = {
  0x00000013, 0x00000000, 0x00000000, 0x00000000, 
  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_0
  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_1
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_2
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_3
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_4
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_5
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_6
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_7
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_8
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_10
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_11
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_12
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_0
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_1
};

static const uint32_t SPRSubClassMask[] = {
  0x00000012, 0x00000000, 0x00000000, 0x00000000, 
  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_0
  0xc0180000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // ssub_1
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_2
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // ssub_3
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_4
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // ssub_5
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_6
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_7
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_8
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_10
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_11
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_12
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_0
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7_then_ssub_1
};

static const uint32_t GPRSubClassMask[] = {
  0x0003bfe4, 0x00000000, 0x00000000, 0x00000000, 
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
};

static const uint32_t GPRwithAPSRSubClassMask[] = {
  0x0002be68, 0x00000000, 0x00000000, 0x00000000, 
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
};

static const uint32_t SPR_8SubClassMask[] = {
  0x00000010, 0x00000000, 0x00000000, 0x00000000, 
  0x00100000, 0xf9300343, 0x3f4901c3, 0x00000078, // ssub_0
  0x00100000, 0xf9300343, 0x3f4901c3, 0x00000078, // ssub_1
  0x00000000, 0x91000300, 0x3d480003, 0x00000078, // ssub_2
  0x00000000, 0x91000300, 0x3d480003, 0x00000078, // ssub_3
  0x00000000, 0x38000002, 0x39400183, 0x00000070, // ssub_4
  0x00000000, 0x38000002, 0x39400183, 0x00000070, // ssub_5
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_6
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_7
  0x00000000, 0x20000000, 0x00000100, 0x00000060, // ssub_8
  0x00000000, 0x20000000, 0x00000100, 0x00000060, // ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_10
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_11
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_12
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_7_then_ssub_0
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_7_then_ssub_1
};

static const uint32_t GPRnopcSubClassMask[] = {
  0x0002be60, 0x00000000, 0x00000000, 0x00000000, 
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
};

static const uint32_t rGPRSubClassMask[] = {
  0x00023a40, 0x00000000, 0x00000000, 0x00000000, 
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
  0x0cc00000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
};

static const uint32_t tGPRwithpcSubClassMask[] = {
  0x00012280, 0x00000000, 0x00000000, 0x00000000, 
  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
};

static const uint32_t hGPRSubClassMask[] = {
  0x00038d00, 0x00000000, 0x00000000, 0x00000000, 
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
};

static const uint32_t tGPRSubClassMask[] = {
  0x00002200, 0x00000000, 0x00000000, 0x00000000, 
  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
  0x08800000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
};

static const uint32_t GPRnopc_and_hGPRSubClassMask[] = {
  0x00028c00, 0x00000000, 0x00000000, 0x00000000, 
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
};

static const uint32_t hGPR_and_rGPRSubClassMask[] = {
  0x00020800, 0x00000000, 0x00000000, 0x00000000, 
  0x15000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
  0x04000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
};

static const uint32_t tcGPRSubClassMask[] = {
  0x00023000, 0x00000000, 0x00000000, 0x00000000, 
  0x1a000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
};

static const uint32_t tGPR_and_tcGPRSubClassMask[] = {
  0x00002000, 0x00000000, 0x00000000, 0x00000000, 
  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
  0x08000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
};

static const uint32_t CCRSubClassMask[] = {
  0x00004000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t GPRspSubClassMask[] = {
  0x00008000, 0x00000000, 0x00000000, 0x00000000, 
  0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_1
};

static const uint32_t hGPR_and_tGPRwithpcSubClassMask[] = {
  0x00010000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t hGPR_and_tcGPRSubClassMask[] = {
  0x00020000, 0x00000000, 0x00000000, 0x00000000, 
  0x10000000, 0x00000000, 0x00000000, 0x00000000, // gsub_0
};

static const uint32_t DPRSubClassMask[] = {
  0x001c0000, 0x00000000, 0x00000000, 0x00000000, 
  0xe0000000, 0xffffffff, 0xffffffff, 0x0000007f, // dsub_0
  0x00000000, 0xd7e5e7fc, 0xfffffe03, 0x0000007f, // dsub_1
  0xe0000000, 0xfffffc03, 0xffffffff, 0x0000007f, // dsub_2
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // dsub_3
  0x00000000, 0x281a1800, 0xc00001fc, 0x0000007f, // dsub_4
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_6
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_7
};

static const uint32_t DPR_VFP2SubClassMask[] = {
  0x00180000, 0x00000000, 0x00000000, 0x00000000, 
  0xc0000000, 0xfffeb3eb, 0xbfffcdfb, 0x0000007f, // dsub_0
  0x00000000, 0xd76483e0, 0xbffbc803, 0x0000007f, // dsub_1
  0x80000000, 0xff3e0003, 0x3ff9c1f3, 0x0000007f, // dsub_2
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // dsub_3
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // dsub_4
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_6
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_7
};

static const uint32_t DPR_8SubClassMask[] = {
  0x00100000, 0x00000000, 0x00000000, 0x00000000, 
  0x00000000, 0xf9300343, 0x3f4901c3, 0x00000078, // dsub_0
  0x00000000, 0x91000300, 0x3d480003, 0x00000078, // dsub_1
  0x00000000, 0x38000002, 0x39400183, 0x00000070, // dsub_2
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // dsub_3
  0x00000000, 0x20000000, 0x00000100, 0x00000060, // dsub_4
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_6
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_7
};

static const uint32_t GPRPairSubClassMask[] = {
  0x1fe00000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t GPRPair_with_gsub_1_in_rGPRSubClassMask[] = {
  0x0cc00000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t GPRPair_with_gsub_0_in_tGPRSubClassMask[] = {
  0x08800000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t GPRPair_with_gsub_0_in_hGPRSubClassMask[] = {
  0x15000000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t GPRPair_with_gsub_0_in_tcGPRSubClassMask[] = {
  0x1a000000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t GPRPair_with_gsub_1_in_hGPR_and_rGPRSubClassMask[] = {
  0x04000000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t GPRPair_with_gsub_1_in_tcGPRSubClassMask[] = {
  0x08000000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t GPRPair_with_gsub_1_in_GPRspSubClassMask[] = {
  0x10000000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t DPairSpcSubClassMask[] = {
  0xe0000000, 0x00000003, 0x00000000, 0x00000000, 
  0x00000000, 0xfffffc00, 0xffffffff, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7
  0x00000000, 0x281a1800, 0xc00001fc, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_dsub_7
};

static const uint32_t DPairSpc_with_ssub_0SubClassMask[] = {
  0xc0000000, 0x00000003, 0x00000000, 0x00000000, 
  0x00000000, 0xfffeb000, 0xbfffcdfb, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5
  0x00000000, 0x00000000, 0xbffbc800, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7
  0x00000000, 0x281a0000, 0x000001f0, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_dsub_7
};

static const uint32_t DPairSpc_with_ssub_4SubClassMask[] = {
  0x80000000, 0x00000003, 0x00000000, 0x00000000, 
  0x00000000, 0xff3e0000, 0x3ff9c1f3, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7
  0x00000000, 0x28180000, 0x000001e0, 0x0000007e, // ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_dsub_7
};

static const uint32_t DPairSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000003, 0x00000000, 0x00000000, 
  0x00000000, 0xf9300000, 0x3f4901c3, 0x00000078, // ssub_0_ssub_1_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x3d480000, 0x00000078, // ssub_2_ssub_3_ssub_6_ssub_7
  0x00000000, 0x28000000, 0x00000180, 0x00000070, // ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_dsub_7
};

static const uint32_t DPairSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000002, 0x00000000, 0x00000000, 
  0x00000000, 0x38000000, 0x39400183, 0x00000070, // ssub_0_ssub_1_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_2_ssub_3_ssub_6_ssub_7
  0x00000000, 0x20000000, 0x00000100, 0x00000060, // ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_dsub_7
};

static const uint32_t DPairSubClassMask[] = {
  0x00000000, 0x000003fc, 0x00000000, 0x00000000, 
  0x00000000, 0xd7e5e400, 0xfffffe03, 0x0000007f, // qsub_0
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // qsub_1
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_2
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_3
  0x00000000, 0xd7e5e400, 0xfffffe03, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_ssub_12_ssub_13
};

static const uint32_t DPair_with_ssub_0SubClassMask[] = {
  0x00000000, 0x000003e8, 0x00000000, 0x00000000, 
  0x00000000, 0xd7e4a000, 0xbfffcc03, 0x0000007f, // qsub_0
  0x00000000, 0x00000000, 0x3ff9c000, 0x0000007f, // qsub_1
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qsub_2
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qsub_3
  0x00000000, 0xd7648000, 0xbffbc803, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_ssub_12_ssub_13
};

static const uint32_t QPRSubClassMask[] = {
  0x00000000, 0x00000290, 0x00000000, 0x00000000, 
  0x00000000, 0x84404000, 0xcc121001, 0x0000007f, // qsub_0
  0x00000000, 0x00000000, 0xcc121000, 0x0000007f, // qsub_1
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_2
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qsub_3
  0x00000000, 0x42810000, 0x32a42002, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
};

static const uint32_t DPair_with_ssub_2SubClassMask[] = {
  0x00000000, 0x000003e0, 0x00000000, 0x00000000, 
  0x00000000, 0xd7648000, 0xbffbc803, 0x0000007f, // qsub_0
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // qsub_1
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qsub_2
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qsub_3
  0x00000000, 0xd7240000, 0x3ff9c003, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13
};

static const uint32_t DPair_with_dsub_0_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000340, 0x00000000, 0x00000000, 
  0x00000000, 0xd1200000, 0x3f490003, 0x00000078, // qsub_0
  0x00000000, 0x00000000, 0x39400000, 0x00000070, // qsub_1
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qsub_2
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qsub_3
  0x00000000, 0x91000000, 0x3d480003, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_ssub_12_ssub_13
};

static const uint32_t QPR_VFP2SubClassMask[] = {
  0x00000000, 0x00000280, 0x00000000, 0x00000000, 
  0x00000000, 0x84400000, 0x8c120001, 0x0000007f, // qsub_0
  0x00000000, 0x00000000, 0x0c100000, 0x0000007f, // qsub_1
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qsub_2
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qsub_3
  0x00000000, 0x42000000, 0x32a00002, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
};

static const uint32_t DPair_with_dsub_1_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000300, 0x00000000, 0x00000000, 
  0x00000000, 0x91000000, 0x3d480003, 0x00000078, // qsub_0
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // qsub_1
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qsub_2
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qsub_3
  0x00000000, 0x10000000, 0x39400003, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13
};

static const uint32_t QPR_8SubClassMask[] = {
  0x00000000, 0x00000200, 0x00000000, 0x00000000, 
  0x00000000, 0x80000000, 0x0c000001, 0x00000078, // qsub_0
  0x00000000, 0x00000000, 0x08000000, 0x00000070, // qsub_1
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qsub_2
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qsub_3
  0x00000000, 0x00000000, 0x30000002, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5
};

static const uint32_t DTripleSubClassMask[] = {
  0x00000000, 0xd7e5e400, 0x00000003, 0x00000000, 
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0xfffffe00, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_ssub_12_ssub_13_dsub_7
};

static const uint32_t DTripleSpcSubClassMask[] = {
  0x00000000, 0x281a1800, 0x000001fc, 0x00000000, 
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DTripleSpc_with_ssub_0SubClassMask[] = {
  0x00000000, 0x281a1000, 0x000001f8, 0x00000000, 
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DTriple_with_ssub_0SubClassMask[] = {
  0x00000000, 0xd7e4a000, 0x00000003, 0x00000000, 
  0x00000000, 0x00000000, 0xbfffcc00, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0xbffbc800, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_ssub_12_ssub_13_dsub_7
};

static const uint32_t DTriple_with_qsub_0_in_QPRSubClassMask[] = {
  0x00000000, 0x84404000, 0x00000001, 0x00000000, 
  0x00000000, 0x00000000, 0xcc121000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x32a42000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
};

static const uint32_t DTriple_with_ssub_2SubClassMask[] = {
  0x00000000, 0xd7648000, 0x00000003, 0x00000000, 
  0x00000000, 0x00000000, 0xbffbc800, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x3ff9c000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13_dsub_7
};

static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
  0x00000000, 0x42810000, 0x00000002, 0x00000000, 
  0x00000000, 0x00000000, 0x32a42000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0xcc121000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // dsub_5_ssub_12_ssub_13_dsub_7
};

static const uint32_t DTripleSpc_with_ssub_4SubClassMask[] = {
  0x00000000, 0x281a0000, 0x000001f0, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DTriple_with_ssub_4SubClassMask[] = {
  0x00000000, 0xd7240000, 0x00000003, 0x00000000, 
  0x00000000, 0x00000000, 0x3ff9c000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x3fd98000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13_dsub_7
};

static const uint32_t DTripleSpc_with_ssub_8SubClassMask[] = {
  0x00000000, 0x28180000, 0x000001e0, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DTripleSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
  0x00000000, 0x28100000, 0x000001c0, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DTriple_with_dsub_0_in_DPR_8SubClassMask[] = {
  0x00000000, 0xd1200000, 0x00000003, 0x00000000, 
  0x00000000, 0x00000000, 0x3f490000, 0x00000078, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x3d480000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_ssub_12_ssub_13_dsub_7
};

static const uint32_t DTriple_with_qsub_0_in_QPR_VFP2SubClassMask[] = {
  0x00000000, 0x84400000, 0x00000001, 0x00000000, 
  0x00000000, 0x00000000, 0x8c120000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x32a00000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
};

static const uint32_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
  0x00000000, 0x42800000, 0x00000002, 0x00000000, 
  0x00000000, 0x00000000, 0x32a40000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x8c120000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // dsub_5_ssub_12_ssub_13_dsub_7
};

static const uint32_t DTriple_with_dsub_1_in_DPR_8SubClassMask[] = {
  0x00000000, 0x91000000, 0x00000003, 0x00000000, 
  0x00000000, 0x00000000, 0x3d480000, 0x00000078, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x39400000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13_dsub_7
};

static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask[] = {
  0x00000000, 0x42000000, 0x00000002, 0x00000000, 
  0x00000000, 0x00000000, 0x32a00000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x0c100000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // dsub_5_ssub_12_ssub_13_dsub_7
};

static const uint32_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSubClassMask[] = {
  0x00000000, 0x84000000, 0x00000001, 0x00000000, 
  0x00000000, 0x00000000, 0x0c100000, 0x0000007f, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x32800000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
};

static const uint32_t DTripleSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
  0x00000000, 0x28000000, 0x00000180, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DTriple_with_dsub_2_in_DPR_8SubClassMask[] = {
  0x00000000, 0x10000000, 0x00000003, 0x00000000, 
  0x00000000, 0x00000000, 0x39400000, 0x00000070, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x29000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13_dsub_7
};

static const uint32_t DTripleSpc_with_dsub_4_in_DPR_8SubClassMask[] = {
  0x00000000, 0x20000000, 0x00000100, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
  0x00000000, 0x40000000, 0x00000002, 0x00000000, 
  0x00000000, 0x00000000, 0x32000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x0c000000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // dsub_5_ssub_12_ssub_13_dsub_7
};

static const uint32_t DTriple_with_qsub_0_in_QPR_8SubClassMask[] = {
  0x00000000, 0x80000000, 0x00000001, 0x00000000, 
  0x00000000, 0x00000000, 0x0c000000, 0x00000078, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x30000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
};

static const uint32_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000001, 0x00000000, 
  0x00000000, 0x00000000, 0x08000000, 0x00000070, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x20000000, 0x00000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
};

static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000002, 0x00000000, 
  0x00000000, 0x00000000, 0x30000000, 0x00000000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
  0x00000000, 0x00000000, 0x08000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // dsub_5_ssub_12_ssub_13_dsub_7
};

static const uint32_t DQuadSpcSubClassMask[] = {
  0x00000000, 0x00000000, 0x000001fc, 0x00000000, 
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DQuadSpc_with_ssub_0SubClassMask[] = {
  0x00000000, 0x00000000, 0x000001f8, 0x00000000, 
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DQuadSpc_with_ssub_4SubClassMask[] = {
  0x00000000, 0x00000000, 0x000001f0, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DQuadSpc_with_ssub_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x000001e0, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DQuadSpc_with_dsub_0_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x000001c0, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DQuadSpc_with_dsub_2_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000180, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DQuadSpc_with_dsub_4_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000100, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_dsub_5_dsub_7
};

static const uint32_t DQuadSubClassMask[] = {
  0x00000000, 0x00000000, 0x3ffffe00, 0x00000000, 
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_0
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_1
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t DQuad_with_ssub_0SubClassMask[] = {
  0x00000000, 0x00000000, 0x3fffcc00, 0x00000000, 
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // qqsub_0
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qqsub_1
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t DQuad_with_ssub_2SubClassMask[] = {
  0x00000000, 0x00000000, 0x3ffbc800, 0x00000000, 
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // qqsub_0
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qqsub_1
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t QQPRSubClassMask[] = {
  0x00000000, 0x00000000, 0x0c121000, 0x00000000, 
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_0
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // qqsub_1
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
  0x00000000, 0x00000000, 0x32a42000, 0x00000000, 
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
};

static const uint32_t DQuad_with_ssub_4SubClassMask[] = {
  0x00000000, 0x00000000, 0x3ff9c000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // qqsub_0
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qqsub_1
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t DQuad_with_ssub_6SubClassMask[] = {
  0x00000000, 0x00000000, 0x3fd98000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // qqsub_0
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qqsub_1
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t DQuad_with_dsub_0_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x3f490000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // qqsub_0
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qqsub_1
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t DQuad_with_qsub_0_in_QPR_VFP2SubClassMask[] = {
  0x00000000, 0x00000000, 0x0c120000, 0x00000000, 
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // qqsub_0
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // qqsub_1
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
  0x00000000, 0x00000000, 0x32a40000, 0x00000000, 
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
};

static const uint32_t DQuad_with_dsub_1_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x3d480000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // qqsub_0
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qqsub_1
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t DQuad_with_qsub_1_in_QPR_VFP2SubClassMask[] = {
  0x00000000, 0x00000000, 0x0c100000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // qqsub_0
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // qqsub_1
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask[] = {
  0x00000000, 0x00000000, 0x32a00000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
};

static const uint32_t DQuad_with_dsub_2_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x39400000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // qqsub_0
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qqsub_1
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
  0x00000000, 0x00000000, 0x32800000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
};

static const uint32_t DQuad_with_dsub_3_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x29000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // qqsub_0
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qqsub_1
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
  0x00000000, 0x00000000, 0x32000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
};

static const uint32_t DQuad_with_qsub_0_in_QPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x0c000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000078, // qqsub_0
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // qqsub_1
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t DQuad_with_qsub_1_in_QPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x08000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // qqsub_0
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // qqsub_1
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
};

static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x30000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000070, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
};

static const uint32_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = {
  0x00000000, 0x00000000, 0x20000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000060, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
};

static const uint32_t QQQQPRSubClassMask[] = {
  0x00000000, 0x00000000, 0xc0000000, 0x0000007f, 
};

static const uint32_t QQQQPR_with_ssub_0SubClassMask[] = {
  0x00000000, 0x00000000, 0x80000000, 0x0000007f, 
};

static const uint32_t QQQQPR_with_ssub_4SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x0000007f, 
};

static const uint32_t QQQQPR_with_ssub_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x0000007e, 
};

static const uint32_t QQQQPR_with_ssub_12SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x0000007c, 
};

static const uint32_t QQQQPR_with_dsub_0_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000078, 
};

static const uint32_t QQQQPR_with_dsub_2_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000070, 
};

static const uint32_t QQQQPR_with_dsub_4_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000060, 
};

static const uint32_t QQQQPR_with_dsub_6_in_DPR_8SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000040, 
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 1, 2, 3, 4, 5, 6, 7, 8, 0,
  /* 9 */ 9, 0,
  /* 11 */ 9, 10, 0,
  /* 14 */ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0,
  /* 31 */ 13, 14, 15, 16, 37, 0,
  /* 37 */ 38, 40, 45, 48, 0,
  /* 42 */ 42, 50, 0,
  /* 45 */ 34, 36, 44, 52, 0,
  /* 50 */ 33, 35, 43, 46, 51, 53, 0,
  /* 57 */ 34, 36, 47, 54, 0,
  /* 62 */ 34, 36, 44, 47, 52, 54, 0,
  /* 69 */ 13, 14, 15, 16, 37, 49, 55, 0,
  /* 77 */ 11, 12, 56, 0,
  /* 81 */ 11, 12, 42, 50, 56, 0,
};

static const TargetRegisterClass *const SPRSuperclasses[] = {
  &ARM::HPRRegClass,
  nullptr
};

static const TargetRegisterClass *const SPR_8Superclasses[] = {
  &ARM::HPRRegClass,
  &ARM::SPRRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRnopcSuperclasses[] = {
  &ARM::GPRRegClass,
  &ARM::GPRwithAPSRRegClass,
  nullptr
};

static const TargetRegisterClass *const rGPRSuperclasses[] = {
  &ARM::GPRRegClass,
  &ARM::GPRwithAPSRRegClass,
  &ARM::GPRnopcRegClass,
  nullptr
};

static const TargetRegisterClass *const tGPRwithpcSuperclasses[] = {
  &ARM::GPRRegClass,
  nullptr
};

static const TargetRegisterClass *const hGPRSuperclasses[] = {
  &ARM::GPRRegClass,
  nullptr
};

static const TargetRegisterClass *const tGPRSuperclasses[] = {
  &ARM::GPRRegClass,
  &ARM::GPRwithAPSRRegClass,
  &ARM::GPRnopcRegClass,
  &ARM::rGPRRegClass,
  &ARM::tGPRwithpcRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRnopc_and_hGPRSuperclasses[] = {
  &ARM::GPRRegClass,
  &ARM::GPRwithAPSRRegClass,
  &ARM::GPRnopcRegClass,
  &ARM::hGPRRegClass,
  nullptr
};

static const TargetRegisterClass *const hGPR_and_rGPRSuperclasses[] = {
  &ARM::GPRRegClass,
  &ARM::GPRwithAPSRRegClass,
  &ARM::GPRnopcRegClass,
  &ARM::rGPRRegClass,
  &ARM::hGPRRegClass,
  &ARM::GPRnopc_and_hGPRRegClass,
  nullptr
};

static const TargetRegisterClass *const tcGPRSuperclasses[] = {
  &ARM::GPRRegClass,
  &ARM::GPRwithAPSRRegClass,
  &ARM::GPRnopcRegClass,
  &ARM::rGPRRegClass,
  nullptr
};

static const TargetRegisterClass *const tGPR_and_tcGPRSuperclasses[] = {
  &ARM::GPRRegClass,
  &ARM::GPRwithAPSRRegClass,
  &ARM::GPRnopcRegClass,
  &ARM::rGPRRegClass,
  &ARM::tGPRwithpcRegClass,
  &ARM::tGPRRegClass,
  &ARM::tcGPRRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRspSuperclasses[] = {
  &ARM::GPRRegClass,
  &ARM::GPRwithAPSRRegClass,
  &ARM::GPRnopcRegClass,
  &ARM::hGPRRegClass,
  &ARM::GPRnopc_and_hGPRRegClass,
  nullptr
};

static const TargetRegisterClass *const hGPR_and_tGPRwithpcSuperclasses[] = {
  &ARM::GPRRegClass,
  &ARM::tGPRwithpcRegClass,
  &ARM::hGPRRegClass,
  nullptr
};

static const TargetRegisterClass *const hGPR_and_tcGPRSuperclasses[] = {
  &ARM::GPRRegClass,
  &ARM::GPRwithAPSRRegClass,
  &ARM::GPRnopcRegClass,
  &ARM::rGPRRegClass,
  &ARM::hGPRRegClass,
  &ARM::GPRnopc_and_hGPRRegClass,
  &ARM::hGPR_and_rGPRRegClass,
  &ARM::tcGPRRegClass,
  nullptr
};

static const TargetRegisterClass *const DPR_VFP2Superclasses[] = {
  &ARM::DPRRegClass,
  nullptr
};

static const TargetRegisterClass *const DPR_8Superclasses[] = {
  &ARM::DPRRegClass,
  &ARM::DPR_VFP2RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_gsub_1_in_rGPRSuperclasses[] = {
  &ARM::GPRPairRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tGPRSuperclasses[] = {
  &ARM::GPRPairRegClass,
  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_gsub_0_in_hGPRSuperclasses[] = {
  &ARM::GPRPairRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tcGPRSuperclasses[] = {
  &ARM::GPRPairRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_gsub_1_in_hGPR_and_rGPRSuperclasses[] = {
  &ARM::GPRPairRegClass,
  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
  &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_gsub_1_in_tcGPRSuperclasses[] = {
  &ARM::GPRPairRegClass,
  &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
  &ARM::GPRPair_with_gsub_0_in_tGPRRegClass,
  &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_gsub_1_in_GPRspSuperclasses[] = {
  &ARM::GPRPairRegClass,
  &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
  &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
  nullptr
};

static const TargetRegisterClass *const DPairSpc_with_ssub_0Superclasses[] = {
  &ARM::DPairSpcRegClass,
  nullptr
};

static const TargetRegisterClass *const DPairSpc_with_ssub_4Superclasses[] = {
  &ARM::DPairSpcRegClass,
  &ARM::DPairSpc_with_ssub_0RegClass,
  nullptr
};

static const TargetRegisterClass *const DPairSpc_with_dsub_0_in_DPR_8Superclasses[] = {
  &ARM::DPairSpcRegClass,
  &ARM::DPairSpc_with_ssub_0RegClass,
  &ARM::DPairSpc_with_ssub_4RegClass,
  nullptr
};

static const TargetRegisterClass *const DPairSpc_with_dsub_2_in_DPR_8Superclasses[] = {
  &ARM::DPairSpcRegClass,
  &ARM::DPairSpc_with_ssub_0RegClass,
  &ARM::DPairSpc_with_ssub_4RegClass,
  &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DPair_with_ssub_0Superclasses[] = {
  &ARM::DPairRegClass,
  nullptr
};

static const TargetRegisterClass *const QPRSuperclasses[] = {
  &ARM::DPairRegClass,
  nullptr
};

static const TargetRegisterClass *const DPair_with_ssub_2Superclasses[] = {
  &ARM::DPairRegClass,
  &ARM::DPair_with_ssub_0RegClass,
  nullptr
};

static const TargetRegisterClass *const DPair_with_dsub_0_in_DPR_8Superclasses[] = {
  &ARM::DPairRegClass,
  &ARM::DPair_with_ssub_0RegClass,
  &ARM::DPair_with_ssub_2RegClass,
  nullptr
};

static const TargetRegisterClass *const QPR_VFP2Superclasses[] = {
  &ARM::DPairRegClass,
  &ARM::DPair_with_ssub_0RegClass,
  &ARM::QPRRegClass,
  &ARM::DPair_with_ssub_2RegClass,
  nullptr
};

static const TargetRegisterClass *const DPair_with_dsub_1_in_DPR_8Superclasses[] = {
  &ARM::DPairRegClass,
  &ARM::DPair_with_ssub_0RegClass,
  &ARM::DPair_with_ssub_2RegClass,
  &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const QPR_8Superclasses[] = {
  &ARM::DPairRegClass,
  &ARM::DPair_with_ssub_0RegClass,
  &ARM::QPRRegClass,
  &ARM::DPair_with_ssub_2RegClass,
  &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
  &ARM::QPR_VFP2RegClass,
  &ARM::DPair_with_dsub_1_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DTripleSpc_with_ssub_0Superclasses[] = {
  &ARM::DTripleSpcRegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_ssub_0Superclasses[] = {
  &ARM::DTripleRegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPRSuperclasses[] = {
  &ARM::DTripleRegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_ssub_2Superclasses[] = {
  &ARM::DTripleRegClass,
  &ARM::DTriple_with_ssub_0RegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
  &ARM::DTripleRegClass,
  nullptr
};

static const TargetRegisterClass *const DTripleSpc_with_ssub_4Superclasses[] = {
  &ARM::DTripleSpcRegClass,
  &ARM::DTripleSpc_with_ssub_0RegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_ssub_4Superclasses[] = {
  &ARM::DTripleRegClass,
  &ARM::DTriple_with_ssub_0RegClass,
  &ARM::DTriple_with_ssub_2RegClass,
  nullptr
};

static const TargetRegisterClass *const DTripleSpc_with_ssub_8Superclasses[] = {
  &ARM::DTripleSpcRegClass,
  &ARM::DTripleSpc_with_ssub_0RegClass,
  &ARM::DTripleSpc_with_ssub_4RegClass,
  nullptr
};

static const TargetRegisterClass *const DTripleSpc_with_dsub_0_in_DPR_8Superclasses[] = {
  &ARM::DTripleSpcRegClass,
  &ARM::DTripleSpc_with_ssub_0RegClass,
  &ARM::DTripleSpc_with_ssub_4RegClass,
  &ARM::DTripleSpc_with_ssub_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8Superclasses[] = {
  &ARM::DTripleRegClass,
  &ARM::DTriple_with_ssub_0RegClass,
  &ARM::DTriple_with_ssub_2RegClass,
  &ARM::DTriple_with_ssub_4RegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_VFP2Superclasses[] = {
  &ARM::DTripleRegClass,
  &ARM::DTriple_with_ssub_0RegClass,
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
  &ARM::DTriple_with_ssub_2RegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
  &ARM::DTripleRegClass,
  &ARM::DTriple_with_ssub_0RegClass,
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_dsub_1_in_DPR_8Superclasses[] = {
  &ARM::DTripleRegClass,
  &ARM::DTriple_with_ssub_0RegClass,
  &ARM::DTriple_with_ssub_2RegClass,
  &ARM::DTriple_with_ssub_4RegClass,
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses[] = {
  &ARM::DTripleRegClass,
  &ARM::DTriple_with_ssub_0RegClass,
  &ARM::DTriple_with_ssub_2RegClass,
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DTriple_with_ssub_4RegClass,
  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSuperclasses[] = {
  &ARM::DTripleRegClass,
  &ARM::DTriple_with_ssub_0RegClass,
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
  &ARM::DTriple_with_ssub_2RegClass,
  &ARM::DTriple_with_ssub_4RegClass,
  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
  nullptr
};

static const TargetRegisterClass *const DTripleSpc_with_dsub_2_in_DPR_8Superclasses[] = {
  &ARM::DTripleSpcRegClass,
  &ARM::DTripleSpc_with_ssub_0RegClass,
  &ARM::DTripleSpc_with_ssub_4RegClass,
  &ARM::DTripleSpc_with_ssub_8RegClass,
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8Superclasses[] = {
  &ARM::DTripleRegClass,
  &ARM::DTriple_with_ssub_0RegClass,
  &ARM::DTriple_with_ssub_2RegClass,
  &ARM::DTriple_with_ssub_4RegClass,
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DTripleSpc_with_dsub_4_in_DPR_8Superclasses[] = {
  &ARM::DTripleSpcRegClass,
  &ARM::DTripleSpc_with_ssub_0RegClass,
  &ARM::DTripleSpc_with_ssub_4RegClass,
  &ARM::DTripleSpc_with_ssub_8RegClass,
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
  &ARM::DTripleRegClass,
  &ARM::DTriple_with_ssub_0RegClass,
  &ARM::DTriple_with_ssub_2RegClass,
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DTriple_with_ssub_4RegClass,
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_8Superclasses[] = {
  &ARM::DTripleRegClass,
  &ARM::DTriple_with_ssub_0RegClass,
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
  &ARM::DTriple_with_ssub_2RegClass,
  &ARM::DTriple_with_ssub_4RegClass,
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
  &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSuperclasses[] = {
  &ARM::DTripleRegClass,
  &ARM::DTriple_with_ssub_0RegClass,
  &ARM::DTriple_with_qsub_0_in_QPRRegClass,
  &ARM::DTriple_with_ssub_2RegClass,
  &ARM::DTriple_with_ssub_4RegClass,
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
  &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
  &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
  &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
  &ARM::DTriple_with_qsub_0_in_QPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
  &ARM::DTripleRegClass,
  &ARM::DTriple_with_ssub_0RegClass,
  &ARM::DTriple_with_ssub_2RegClass,
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DTriple_with_ssub_4RegClass,
  &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
  &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
  &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
  &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
  &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  nullptr
};

static const TargetRegisterClass *const DQuadSpcSuperclasses[] = {
  &ARM::DTripleSpcRegClass,
  nullptr
};

static const TargetRegisterClass *const DQuadSpc_with_ssub_0Superclasses[] = {
  &ARM::DTripleSpcRegClass,
  &ARM::DTripleSpc_with_ssub_0RegClass,
  &ARM::DQuadSpcRegClass,
  nullptr
};

static const TargetRegisterClass *const DQuadSpc_with_ssub_4Superclasses[] = {
  &ARM::DTripleSpcRegClass,
  &ARM::DTripleSpc_with_ssub_0RegClass,
  &ARM::DTripleSpc_with_ssub_4RegClass,
  &ARM::DQuadSpcRegClass,
  &ARM::DQuadSpc_with_ssub_0RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuadSpc_with_ssub_8Superclasses[] = {
  &ARM::DTripleSpcRegClass,
  &ARM::DTripleSpc_with_ssub_0RegClass,
  &ARM::DTripleSpc_with_ssub_4RegClass,
  &ARM::DTripleSpc_with_ssub_8RegClass,
  &ARM::DQuadSpcRegClass,
  &ARM::DQuadSpc_with_ssub_0RegClass,
  &ARM::DQuadSpc_with_ssub_4RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuadSpc_with_dsub_0_in_DPR_8Superclasses[] = {
  &ARM::DTripleSpcRegClass,
  &ARM::DTripleSpc_with_ssub_0RegClass,
  &ARM::DTripleSpc_with_ssub_4RegClass,
  &ARM::DTripleSpc_with_ssub_8RegClass,
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
  &ARM::DQuadSpcRegClass,
  &ARM::DQuadSpc_with_ssub_0RegClass,
  &ARM::DQuadSpc_with_ssub_4RegClass,
  &ARM::DQuadSpc_with_ssub_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuadSpc_with_dsub_2_in_DPR_8Superclasses[] = {
  &ARM::DTripleSpcRegClass,
  &ARM::DTripleSpc_with_ssub_0RegClass,
  &ARM::DTripleSpc_with_ssub_4RegClass,
  &ARM::DTripleSpc_with_ssub_8RegClass,
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
  &ARM::DQuadSpcRegClass,
  &ARM::DQuadSpc_with_ssub_0RegClass,
  &ARM::DQuadSpc_with_ssub_4RegClass,
  &ARM::DQuadSpc_with_ssub_8RegClass,
  &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuadSpc_with_dsub_4_in_DPR_8Superclasses[] = {
  &ARM::DTripleSpcRegClass,
  &ARM::DTripleSpc_with_ssub_0RegClass,
  &ARM::DTripleSpc_with_ssub_4RegClass,
  &ARM::DTripleSpc_with_ssub_8RegClass,
  &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
  &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
  &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass,
  &ARM::DQuadSpcRegClass,
  &ARM::DQuadSpc_with_ssub_0RegClass,
  &ARM::DQuadSpc_with_ssub_4RegClass,
  &ARM::DQuadSpc_with_ssub_8RegClass,
  &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
  &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_ssub_0Superclasses[] = {
  &ARM::DQuadRegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_ssub_2Superclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  nullptr
};

static const TargetRegisterClass *const QQPRSuperclasses[] = {
  &ARM::DQuadRegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
  &ARM::DQuadRegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_ssub_4Superclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_ssub_6Superclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::DQuad_with_ssub_4RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8Superclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::DQuad_with_ssub_4RegClass,
  &ARM::DQuad_with_ssub_6RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_VFP2Superclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::QQPRRegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_dsub_1_in_DPR_8Superclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::DQuad_with_ssub_4RegClass,
  &ARM::DQuad_with_ssub_6RegClass,
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_VFP2Superclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::QQPRRegClass,
  &ARM::DQuad_with_ssub_4RegClass,
  &ARM::DQuad_with_ssub_6RegClass,
  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DQuad_with_ssub_4RegClass,
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_dsub_2_in_DPR_8Superclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::DQuad_with_ssub_4RegClass,
  &ARM::DQuad_with_ssub_6RegClass,
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DQuad_with_ssub_4RegClass,
  &ARM::DQuad_with_ssub_6RegClass,
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8Superclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::DQuad_with_ssub_4RegClass,
  &ARM::DQuad_with_ssub_6RegClass,
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DQuad_with_ssub_4RegClass,
  &ARM::DQuad_with_ssub_6RegClass,
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
  &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_8Superclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::QQPRRegClass,
  &ARM::DQuad_with_ssub_4RegClass,
  &ARM::DQuad_with_ssub_6RegClass,
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
  &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_8Superclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::QQPRRegClass,
  &ARM::DQuad_with_ssub_4RegClass,
  &ARM::DQuad_with_ssub_6RegClass,
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
  &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
  &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
  &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
  &ARM::DQuad_with_qsub_0_in_QPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DQuad_with_ssub_4RegClass,
  &ARM::DQuad_with_ssub_6RegClass,
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
  &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  nullptr
};

static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
  &ARM::DQuadRegClass,
  &ARM::DQuad_with_ssub_0RegClass,
  &ARM::DQuad_with_ssub_2RegClass,
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DQuad_with_ssub_4RegClass,
  &ARM::DQuad_with_ssub_6RegClass,
  &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
  &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
  &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
  &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
  &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
  &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const QQQQPR_with_ssub_0Superclasses[] = {
  &ARM::QQQQPRRegClass,
  nullptr
};

static const TargetRegisterClass *const QQQQPR_with_ssub_4Superclasses[] = {
  &ARM::QQQQPRRegClass,
  &ARM::QQQQPR_with_ssub_0RegClass,
  nullptr
};

static const TargetRegisterClass *const QQQQPR_with_ssub_8Superclasses[] = {
  &ARM::QQQQPRRegClass,
  &ARM::QQQQPR_with_ssub_0RegClass,
  &ARM::QQQQPR_with_ssub_4RegClass,
  nullptr
};

static const TargetRegisterClass *const QQQQPR_with_ssub_12Superclasses[] = {
  &ARM::QQQQPRRegClass,
  &ARM::QQQQPR_with_ssub_0RegClass,
  &ARM::QQQQPR_with_ssub_4RegClass,
  &ARM::QQQQPR_with_ssub_8RegClass,
  nullptr
};

static const TargetRegisterClass *const QQQQPR_with_dsub_0_in_DPR_8Superclasses[] = {
  &ARM::QQQQPRRegClass,
  &ARM::QQQQPR_with_ssub_0RegClass,
  &ARM::QQQQPR_with_ssub_4RegClass,
  &ARM::QQQQPR_with_ssub_8RegClass,
  &ARM::QQQQPR_with_ssub_12RegClass,
  nullptr
};

static const TargetRegisterClass *const QQQQPR_with_dsub_2_in_DPR_8Superclasses[] = {
  &ARM::QQQQPRRegClass,
  &ARM::QQQQPR_with_ssub_0RegClass,
  &ARM::QQQQPR_with_ssub_4RegClass,
  &ARM::QQQQPR_with_ssub_8RegClass,
  &ARM::QQQQPR_with_ssub_12RegClass,
  &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const QQQQPR_with_dsub_4_in_DPR_8Superclasses[] = {
  &ARM::QQQQPRRegClass,
  &ARM::QQQQPR_with_ssub_0RegClass,
  &ARM::QQQQPR_with_ssub_4RegClass,
  &ARM::QQQQPR_with_ssub_8RegClass,
  &ARM::QQQQPR_with_ssub_12RegClass,
  &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
  &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass,
  nullptr
};

static const TargetRegisterClass *const QQQQPR_with_dsub_6_in_DPR_8Superclasses[] = {
  &ARM::QQQQPRRegClass,
  &ARM::QQQQPR_with_ssub_0RegClass,
  &ARM::QQQQPR_with_ssub_4RegClass,
  &ARM::QQQQPR_with_ssub_8RegClass,
  &ARM::QQQQPR_with_ssub_12RegClass,
  &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
  &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass,
  &ARM::QQQQPR_with_dsub_4_in_DPR_8RegClass,
  nullptr
};


static inline unsigned HPRAltOrderSelect(const MachineFunction &MF) {
    return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
  }

static ArrayRef<MCPhysReg> HPRGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::S0, ARM::S2, ARM::S4, ARM::S6, ARM::S8, ARM::S10, ARM::S12, ARM::S14, ARM::S16, ARM::S18, ARM::S20, ARM::S22, ARM::S24, ARM::S26, ARM::S28, ARM::S30, ARM::S1, ARM::S3, ARM::S5, ARM::S7, ARM::S9, ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29, ARM::S31 };
  static const MCPhysReg AltOrder2[] = { ARM::S0, ARM::S4, ARM::S8, ARM::S12, ARM::S16, ARM::S20, ARM::S24, ARM::S28, ARM::S2, ARM::S6, ARM::S10, ARM::S14, ARM::S18, ARM::S22, ARM::S26, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3, ARM::S7, ARM::S11, ARM::S15, ARM::S19, ARM::S23, ARM::S27, ARM::S31 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::HPRRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1),
    makeArrayRef(AltOrder2)
  };
  const unsigned Select = HPRAltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

static inline unsigned SPRAltOrderSelect(const MachineFunction &MF) {
    return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
  }

static ArrayRef<MCPhysReg> SPRGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::S0, ARM::S2, ARM::S4, ARM::S6, ARM::S8, ARM::S10, ARM::S12, ARM::S14, ARM::S16, ARM::S18, ARM::S20, ARM::S22, ARM::S24, ARM::S26, ARM::S28, ARM::S30, ARM::S1, ARM::S3, ARM::S5, ARM::S7, ARM::S9, ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29, ARM::S31 };
  static const MCPhysReg AltOrder2[] = { ARM::S0, ARM::S4, ARM::S8, ARM::S12, ARM::S16, ARM::S20, ARM::S24, ARM::S28, ARM::S2, ARM::S6, ARM::S10, ARM::S14, ARM::S18, ARM::S22, ARM::S26, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3, ARM::S7, ARM::S11, ARM::S15, ARM::S19, ARM::S23, ARM::S27, ARM::S31 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::SPRRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1),
    makeArrayRef(AltOrder2)
  };
  const unsigned Select = SPRAltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

static inline unsigned GPRAltOrderSelect(const MachineFunction &MF) {
      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
  }

static ArrayRef<MCPhysReg> GPRGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::PC };
  static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1),
    makeArrayRef(AltOrder2)
  };
  const unsigned Select = GPRAltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

static inline unsigned GPRwithAPSRAltOrderSelect(const MachineFunction &MF) {
      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
  }

static ArrayRef<MCPhysReg> GPRwithAPSRGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
  static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithAPSRRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1),
    makeArrayRef(AltOrder2)
  };
  const unsigned Select = GPRwithAPSRAltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

static inline unsigned GPRnopcAltOrderSelect(const MachineFunction &MF) {
      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
  }

static ArrayRef<MCPhysReg> GPRnopcGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
  static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRnopcRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1),
    makeArrayRef(AltOrder2)
  };
  const unsigned Select = GPRnopcAltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

static inline unsigned rGPRAltOrderSelect(const MachineFunction &MF) {
      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
  }

static ArrayRef<MCPhysReg> rGPRGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12 };
  static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::rGPRRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1),
    makeArrayRef(AltOrder2)
  };
  const unsigned Select = rGPRAltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

static inline unsigned tcGPRAltOrderSelect(const MachineFunction &MF) {
      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
  }

static ArrayRef<MCPhysReg> tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tcGPRRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = tcGPRAltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned tGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) {
      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
  }

static ArrayRef<MCPhysReg> tGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPR_and_tcGPRRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = tGPR_and_tcGPRAltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned hGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) {
      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
  }

static ArrayRef<MCPhysReg> hGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) {
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::hGPR_and_tcGPRRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef<MCPhysReg>()
  };
  const unsigned Select = hGPR_and_tcGPRAltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned DPRAltOrderSelect(const MachineFunction &MF) {
    return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(MF);
  }

static ArrayRef<MCPhysReg> DPRGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
  static const MCPhysReg AltOrder2[] = { ARM::D16, ARM::D18, ARM::D20, ARM::D22, ARM::D24, ARM::D26, ARM::D28, ARM::D30, ARM::D0, ARM::D2, ARM::D4, ARM::D6, ARM::D8, ARM::D10, ARM::D12, ARM::D14, ARM::D17, ARM::D19, ARM::D21, ARM::D23, ARM::D25, ARM::D27, ARM::D29, ARM::D31, ARM::D1, ARM::D3, ARM::D5, ARM::D7, ARM::D9, ARM::D11, ARM::D13, ARM::D15 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPRRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1),
    makeArrayRef(AltOrder2)
  };
  const unsigned Select = DPRAltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

static inline unsigned DPairAltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> DPairGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D17_D18, ARM::D19_D20, ARM::D21_D22, ARM::D23_D24, ARM::D25_D26, ARM::D27_D28, ARM::D29_D30, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPairRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = DPairAltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned DPair_with_ssub_0AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> DPair_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_0RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = DPair_with_ssub_0AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned QPRAltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> QPRGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QPRRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = QPRAltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned DPair_with_ssub_2AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> DPair_with_ssub_2GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_2RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = DPair_with_ssub_2AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned DPair_with_dsub_0_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> DPair_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_0_in_DPR_8RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = DPair_with_dsub_0_in_DPR_8AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned DPair_with_dsub_1_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> DPair_with_dsub_1_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_1_in_DPR_8RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = DPair_with_dsub_1_in_DPR_8AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned QQPRAltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> QQPRGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQPRRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = QQPRAltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned DQuad_with_qsub_0_in_QPR_VFP2AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_QPR_VFP2GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = DQuad_with_qsub_0_in_QPR_VFP2AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned DQuad_with_qsub_1_in_QPR_VFP2AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_QPR_VFP2GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = DQuad_with_qsub_1_in_QPR_VFP2AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned DQuad_with_qsub_0_in_QPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_QPR_8RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = DQuad_with_qsub_0_in_QPR_8AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned DQuad_with_qsub_1_in_QPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_QPR_8RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = DQuad_with_qsub_1_in_QPR_8AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned QQQQPRAltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> QQQQPRGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPRRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = QQQQPRAltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned QQQQPR_with_ssub_0AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> QQQQPR_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_0RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = QQQQPR_with_ssub_0AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned QQQQPR_with_ssub_4AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> QQQQPR_with_ssub_4GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_4RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = QQQQPR_with_ssub_4AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned QQQQPR_with_ssub_8AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> QQQQPR_with_ssub_8GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_8RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = QQQQPR_with_ssub_8AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned QQQQPR_with_ssub_12AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> QQQQPR_with_ssub_12GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_12RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = QQQQPR_with_ssub_12AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned QQQQPR_with_dsub_0_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> QQQQPR_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = QQQQPR_with_dsub_0_in_DPR_8AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned QQQQPR_with_dsub_2_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> QQQQPR_with_dsub_2_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = QQQQPR_with_dsub_2_in_DPR_8AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned QQQQPR_with_dsub_4_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> QQQQPR_with_dsub_4_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = QQQQPR_with_dsub_4_in_DPR_8AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned QQQQPR_with_dsub_6_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; }

static ArrayRef<MCPhysReg> QQQQPR_with_dsub_6_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3 };
  const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = QQQQPR_with_dsub_6_in_DPR_8AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

namespace ARM {   // Register class instances
  extern const TargetRegisterClass HPRRegClass = {
    &ARMMCRegisterClasses[HPRRegClassID],
    HPRSubClassMask,
    SuperRegIdxSeqs + 14,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    HPRGetRawAllocationOrder
  };

  extern const TargetRegisterClass SPRRegClass = {
    &ARMMCRegisterClasses[SPRRegClassID],
    SPRSubClassMask,
    SuperRegIdxSeqs + 14,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    SPRSuperclasses,
    SPRGetRawAllocationOrder
  };

  extern const TargetRegisterClass GPRRegClass = {
    &ARMMCRegisterClasses[GPRRegClassID],
    GPRSubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    GPRGetRawAllocationOrder
  };

  extern const TargetRegisterClass GPRwithAPSRRegClass = {
    &ARMMCRegisterClasses[GPRwithAPSRRegClassID],
    GPRwithAPSRSubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    GPRwithAPSRGetRawAllocationOrder
  };

  extern const TargetRegisterClass SPR_8RegClass = {
    &ARMMCRegisterClasses[SPR_8RegClassID],
    SPR_8SubClassMask,
    SuperRegIdxSeqs + 14,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    SPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRnopcRegClass = {
    &ARMMCRegisterClasses[GPRnopcRegClassID],
    GPRnopcSubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRnopcSuperclasses,
    GPRnopcGetRawAllocationOrder
  };

  extern const TargetRegisterClass rGPRRegClass = {
    &ARMMCRegisterClasses[rGPRRegClassID],
    rGPRSubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    rGPRSuperclasses,
    rGPRGetRawAllocationOrder
  };

  extern const TargetRegisterClass tGPRwithpcRegClass = {
    &ARMMCRegisterClasses[tGPRwithpcRegClassID],
    tGPRwithpcSubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    tGPRwithpcSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass hGPRRegClass = {
    &ARMMCRegisterClasses[hGPRRegClassID],
    hGPRSubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    hGPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass tGPRRegClass = {
    &ARMMCRegisterClasses[tGPRRegClassID],
    tGPRSubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    tGPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRnopc_and_hGPRRegClass = {
    &ARMMCRegisterClasses[GPRnopc_and_hGPRRegClassID],
    GPRnopc_and_hGPRSubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRnopc_and_hGPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass hGPR_and_rGPRRegClass = {
    &ARMMCRegisterClasses[hGPR_and_rGPRRegClassID],
    hGPR_and_rGPRSubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    hGPR_and_rGPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass tcGPRRegClass = {
    &ARMMCRegisterClasses[tcGPRRegClassID],
    tcGPRSubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    tcGPRSuperclasses,
    tcGPRGetRawAllocationOrder
  };

  extern const TargetRegisterClass tGPR_and_tcGPRRegClass = {
    &ARMMCRegisterClasses[tGPR_and_tcGPRRegClassID],
    tGPR_and_tcGPRSubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    tGPR_and_tcGPRSuperclasses,
    tGPR_and_tcGPRGetRawAllocationOrder
  };

  extern const TargetRegisterClass CCRRegClass = {
    &ARMMCRegisterClasses[CCRRegClassID],
    CCRSubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPRspRegClass = {
    &ARMMCRegisterClasses[GPRspRegClassID],
    GPRspSubClassMask,
    SuperRegIdxSeqs + 12,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRspSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass = {
    &ARMMCRegisterClasses[hGPR_and_tGPRwithpcRegClassID],
    hGPR_and_tGPRwithpcSubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    hGPR_and_tGPRwithpcSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass hGPR_and_tcGPRRegClass = {
    &ARMMCRegisterClasses[hGPR_and_tcGPRRegClassID],
    hGPR_and_tcGPRSubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    hGPR_and_tcGPRSuperclasses,
    hGPR_and_tcGPRGetRawAllocationOrder
  };

  extern const TargetRegisterClass DPRRegClass = {
    &ARMMCRegisterClasses[DPRRegClassID],
    DPRSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000C),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    DPRGetRawAllocationOrder
  };

  extern const TargetRegisterClass DPR_VFP2RegClass = {
    &ARMMCRegisterClasses[DPR_VFP2RegClassID],
    DPR_VFP2SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000C),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DPR_VFP2Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DPR_8RegClass = {
    &ARMMCRegisterClasses[DPR_8RegClassID],
    DPR_8SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000C),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPairRegClass = {
    &ARMMCRegisterClasses[GPRPairRegClassID],
    GPRPairSubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_gsub_1_in_rGPRRegClass = {
    &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_rGPRRegClassID],
    GPRPair_with_gsub_1_in_rGPRSubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_gsub_1_in_rGPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass = {
    &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_tGPRRegClassID],
    GPRPair_with_gsub_0_in_tGPRSubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_gsub_0_in_tGPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass = {
    &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_hGPRRegClassID],
    GPRPair_with_gsub_0_in_hGPRSubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_gsub_0_in_hGPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass = {
    &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_tcGPRRegClassID],
    GPRPair_with_gsub_0_in_tcGPRSubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_gsub_0_in_tcGPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass = {
    &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID],
    GPRPair_with_gsub_1_in_hGPR_and_rGPRSubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_gsub_1_in_hGPR_and_rGPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass = {
    &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_tcGPRRegClassID],
    GPRPair_with_gsub_1_in_tcGPRSubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_gsub_1_in_tcGPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass = {
    &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_GPRspRegClassID],
    GPRPair_with_gsub_1_in_GPRspSubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_gsub_1_in_GPRspSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DPairSpcRegClass = {
    &ARMMCRegisterClasses[DPairSpcRegClassID],
    DPairSpcSubClassMask,
    SuperRegIdxSeqs + 50,
    LaneBitmask(0x000000CC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass = {
    &ARMMCRegisterClasses[DPairSpc_with_ssub_0RegClassID],
    DPairSpc_with_ssub_0SubClassMask,
    SuperRegIdxSeqs + 50,
    LaneBitmask(0x000000CC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DPairSpc_with_ssub_0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass = {
    &ARMMCRegisterClasses[DPairSpc_with_ssub_4RegClassID],
    DPairSpc_with_ssub_4SubClassMask,
    SuperRegIdxSeqs + 50,
    LaneBitmask(0x000000CC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DPairSpc_with_ssub_4Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DPairSpc_with_dsub_0_in_DPR_8RegClassID],
    DPairSpc_with_dsub_0_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 50,
    LaneBitmask(0x000000CC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DPairSpc_with_dsub_0_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DPairSpc_with_dsub_2_in_DPR_8RegClassID],
    DPairSpc_with_dsub_2_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 50,
    LaneBitmask(0x000000CC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DPairSpc_with_dsub_2_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DPairRegClass = {
    &ARMMCRegisterClasses[DPairRegClassID],
    DPairSubClassMask,
    SuperRegIdxSeqs + 69,
    LaneBitmask(0x0000003C),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    DPairGetRawAllocationOrder
  };

  extern const TargetRegisterClass DPair_with_ssub_0RegClass = {
    &ARMMCRegisterClasses[DPair_with_ssub_0RegClassID],
    DPair_with_ssub_0SubClassMask,
    SuperRegIdxSeqs + 69,
    LaneBitmask(0x0000003C),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DPair_with_ssub_0Superclasses,
    DPair_with_ssub_0GetRawAllocationOrder
  };

  extern const TargetRegisterClass QPRRegClass = {
    &ARMMCRegisterClasses[QPRRegClassID],
    QPRSubClassMask,
    SuperRegIdxSeqs + 31,
    LaneBitmask(0x0000003C),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    QPRSuperclasses,
    QPRGetRawAllocationOrder
  };

  extern const TargetRegisterClass DPair_with_ssub_2RegClass = {
    &ARMMCRegisterClasses[DPair_with_ssub_2RegClassID],
    DPair_with_ssub_2SubClassMask,
    SuperRegIdxSeqs + 69,
    LaneBitmask(0x0000003C),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DPair_with_ssub_2Superclasses,
    DPair_with_ssub_2GetRawAllocationOrder
  };

  extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DPair_with_dsub_0_in_DPR_8RegClassID],
    DPair_with_dsub_0_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 69,
    LaneBitmask(0x0000003C),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DPair_with_dsub_0_in_DPR_8Superclasses,
    DPair_with_dsub_0_in_DPR_8GetRawAllocationOrder
  };

  extern const TargetRegisterClass QPR_VFP2RegClass = {
    &ARMMCRegisterClasses[QPR_VFP2RegClassID],
    QPR_VFP2SubClassMask,
    SuperRegIdxSeqs + 31,
    LaneBitmask(0x0000003C),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    QPR_VFP2Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DPair_with_dsub_1_in_DPR_8RegClassID],
    DPair_with_dsub_1_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 69,
    LaneBitmask(0x0000003C),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DPair_with_dsub_1_in_DPR_8Superclasses,
    DPair_with_dsub_1_in_DPR_8GetRawAllocationOrder
  };

  extern const TargetRegisterClass QPR_8RegClass = {
    &ARMMCRegisterClasses[QPR_8RegClassID],
    QPR_8SubClassMask,
    SuperRegIdxSeqs + 31,
    LaneBitmask(0x0000003C),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    QPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTripleRegClass = {
    &ARMMCRegisterClasses[DTripleRegClassID],
    DTripleSubClassMask,
    SuperRegIdxSeqs + 62,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass DTripleSpcRegClass = {
    &ARMMCRegisterClasses[DTripleSpcRegClassID],
    DTripleSpcSubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass = {
    &ARMMCRegisterClasses[DTripleSpc_with_ssub_0RegClassID],
    DTripleSpc_with_ssub_0SubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTripleSpc_with_ssub_0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_ssub_0RegClass = {
    &ARMMCRegisterClasses[DTriple_with_ssub_0RegClassID],
    DTriple_with_ssub_0SubClassMask,
    SuperRegIdxSeqs + 62,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_ssub_0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass = {
    &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPRRegClassID],
    DTriple_with_qsub_0_in_QPRSubClassMask,
    SuperRegIdxSeqs + 45,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_qsub_0_in_QPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_ssub_2RegClass = {
    &ARMMCRegisterClasses[DTriple_with_ssub_2RegClassID],
    DTriple_with_ssub_2SubClassMask,
    SuperRegIdxSeqs + 62,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_ssub_2Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    SuperRegIdxSeqs + 57,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass = {
    &ARMMCRegisterClasses[DTripleSpc_with_ssub_4RegClassID],
    DTripleSpc_with_ssub_4SubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTripleSpc_with_ssub_4Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_ssub_4RegClass = {
    &ARMMCRegisterClasses[DTriple_with_ssub_4RegClassID],
    DTriple_with_ssub_4SubClassMask,
    SuperRegIdxSeqs + 62,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_ssub_4Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass = {
    &ARMMCRegisterClasses[DTripleSpc_with_ssub_8RegClassID],
    DTripleSpc_with_ssub_8SubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTripleSpc_with_ssub_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DTripleSpc_with_dsub_0_in_DPR_8RegClassID],
    DTripleSpc_with_dsub_0_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTripleSpc_with_dsub_0_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DTriple_with_dsub_0_in_DPR_8RegClassID],
    DTriple_with_dsub_0_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 62,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_dsub_0_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_VFP2RegClass = {
    &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPR_VFP2RegClassID],
    DTriple_with_qsub_0_in_QPR_VFP2SubClassMask,
    SuperRegIdxSeqs + 45,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_qsub_0_in_QPR_VFP2Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    &ARMMCRegisterClasses[DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    SuperRegIdxSeqs + 57,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DTriple_with_dsub_1_in_DPR_8RegClassID],
    DTriple_with_dsub_1_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 62,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_dsub_1_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass = {
    &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID],
    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask,
    SuperRegIdxSeqs + 57,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass = {
    &ARMMCRegisterClasses[DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID],
    DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSubClassMask,
    SuperRegIdxSeqs + 45,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DTripleSpc_with_dsub_2_in_DPR_8RegClassID],
    DTripleSpc_with_dsub_2_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTripleSpc_with_dsub_2_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DTriple_with_dsub_2_in_DPR_8RegClassID],
    DTriple_with_dsub_2_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 62,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_dsub_2_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DTripleSpc_with_dsub_4_in_DPR_8RegClassID],
    DTripleSpc_with_dsub_4_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTripleSpc_with_dsub_4_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    &ARMMCRegisterClasses[DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    SuperRegIdxSeqs + 57,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass = {
    &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPR_8RegClassID],
    DTriple_with_qsub_0_in_QPR_8SubClassMask,
    SuperRegIdxSeqs + 45,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_qsub_0_in_QPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass = {
    &ARMMCRegisterClasses[DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID],
    DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSubClassMask,
    SuperRegIdxSeqs + 45,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = {
    &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID],
    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask,
    SuperRegIdxSeqs + 57,
    LaneBitmask(0x000000FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuadSpcRegClass = {
    &ARMMCRegisterClasses[DQuadSpcRegClassID],
    DQuadSpcSubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuadSpcSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass = {
    &ARMMCRegisterClasses[DQuadSpc_with_ssub_0RegClassID],
    DQuadSpc_with_ssub_0SubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuadSpc_with_ssub_0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass = {
    &ARMMCRegisterClasses[DQuadSpc_with_ssub_4RegClassID],
    DQuadSpc_with_ssub_4SubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuadSpc_with_ssub_4Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass = {
    &ARMMCRegisterClasses[DQuadSpc_with_ssub_8RegClassID],
    DQuadSpc_with_ssub_8SubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuadSpc_with_ssub_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DQuadSpc_with_dsub_0_in_DPR_8RegClassID],
    DQuadSpc_with_dsub_0_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuadSpc_with_dsub_0_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DQuadSpc_with_dsub_2_in_DPR_8RegClassID],
    DQuadSpc_with_dsub_2_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuadSpc_with_dsub_2_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DQuadSpc_with_dsub_4_in_DPR_8RegClassID],
    DQuadSpc_with_dsub_4_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 37,
    LaneBitmask(0x00000CCC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuadSpc_with_dsub_4_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuadRegClass = {
    &ARMMCRegisterClasses[DQuadRegClassID],
    DQuadSubClassMask,
    SuperRegIdxSeqs + 81,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_ssub_0RegClass = {
    &ARMMCRegisterClasses[DQuad_with_ssub_0RegClassID],
    DQuad_with_ssub_0SubClassMask,
    SuperRegIdxSeqs + 81,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_ssub_0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_ssub_2RegClass = {
    &ARMMCRegisterClasses[DQuad_with_ssub_2RegClassID],
    DQuad_with_ssub_2SubClassMask,
    SuperRegIdxSeqs + 81,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_ssub_2Superclasses,
    nullptr
  };

  extern const TargetRegisterClass QQPRRegClass = {
    &ARMMCRegisterClasses[QQPRRegClassID],
    QQPRSubClassMask,
    SuperRegIdxSeqs + 77,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    QQPRSuperclasses,
    QQPRGetRawAllocationOrder
  };

  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    SuperRegIdxSeqs + 42,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_ssub_4RegClass = {
    &ARMMCRegisterClasses[DQuad_with_ssub_4RegClassID],
    DQuad_with_ssub_4SubClassMask,
    SuperRegIdxSeqs + 81,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_ssub_4Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_ssub_6RegClass = {
    &ARMMCRegisterClasses[DQuad_with_ssub_6RegClassID],
    DQuad_with_ssub_6SubClassMask,
    SuperRegIdxSeqs + 81,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_ssub_6Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DQuad_with_dsub_0_in_DPR_8RegClassID],
    DQuad_with_dsub_0_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 81,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_dsub_0_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_VFP2RegClass = {
    &ARMMCRegisterClasses[DQuad_with_qsub_0_in_QPR_VFP2RegClassID],
    DQuad_with_qsub_0_in_QPR_VFP2SubClassMask,
    SuperRegIdxSeqs + 77,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_qsub_0_in_QPR_VFP2Superclasses,
    DQuad_with_qsub_0_in_QPR_VFP2GetRawAllocationOrder
  };

  extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    &ARMMCRegisterClasses[DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    SuperRegIdxSeqs + 42,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DQuad_with_dsub_1_in_DPR_8RegClassID],
    DQuad_with_dsub_1_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 81,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_dsub_1_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_VFP2RegClass = {
    &ARMMCRegisterClasses[DQuad_with_qsub_1_in_QPR_VFP2RegClassID],
    DQuad_with_qsub_1_in_QPR_VFP2SubClassMask,
    SuperRegIdxSeqs + 77,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_qsub_1_in_QPR_VFP2Superclasses,
    DQuad_with_qsub_1_in_QPR_VFP2GetRawAllocationOrder
  };

  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass = {
    &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID],
    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2SubClassMask,
    SuperRegIdxSeqs + 42,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DQuad_with_dsub_2_in_DPR_8RegClassID],
    DQuad_with_dsub_2_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 81,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_dsub_2_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    &ARMMCRegisterClasses[DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    SuperRegIdxSeqs + 42,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[DQuad_with_dsub_3_in_DPR_8RegClassID],
    DQuad_with_dsub_3_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 81,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_dsub_3_in_DPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    &ARMMCRegisterClasses[DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    SuperRegIdxSeqs + 42,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass = {
    &ARMMCRegisterClasses[DQuad_with_qsub_0_in_QPR_8RegClassID],
    DQuad_with_qsub_0_in_QPR_8SubClassMask,
    SuperRegIdxSeqs + 77,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_qsub_0_in_QPR_8Superclasses,
    DQuad_with_qsub_0_in_QPR_8GetRawAllocationOrder
  };

  extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass = {
    &ARMMCRegisterClasses[DQuad_with_qsub_1_in_QPR_8RegClassID],
    DQuad_with_qsub_1_in_QPR_8SubClassMask,
    SuperRegIdxSeqs + 77,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_qsub_1_in_QPR_8Superclasses,
    DQuad_with_qsub_1_in_QPR_8GetRawAllocationOrder
  };

  extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = {
    &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID],
    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask,
    SuperRegIdxSeqs + 42,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
    &ARMMCRegisterClasses[DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID],
    DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask,
    SuperRegIdxSeqs + 42,
    LaneBitmask(0x000003FC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass QQQQPRRegClass = {
    &ARMMCRegisterClasses[QQQQPRRegClassID],
    QQQQPRSubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x0003FFFC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    QQQQPRGetRawAllocationOrder
  };

  extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass = {
    &ARMMCRegisterClasses[QQQQPR_with_ssub_0RegClassID],
    QQQQPR_with_ssub_0SubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x0003FFFC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    QQQQPR_with_ssub_0Superclasses,
    QQQQPR_with_ssub_0GetRawAllocationOrder
  };

  extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass = {
    &ARMMCRegisterClasses[QQQQPR_with_ssub_4RegClassID],
    QQQQPR_with_ssub_4SubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x0003FFFC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    QQQQPR_with_ssub_4Superclasses,
    QQQQPR_with_ssub_4GetRawAllocationOrder
  };

  extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass = {
    &ARMMCRegisterClasses[QQQQPR_with_ssub_8RegClassID],
    QQQQPR_with_ssub_8SubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x0003FFFC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    QQQQPR_with_ssub_8Superclasses,
    QQQQPR_with_ssub_8GetRawAllocationOrder
  };

  extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass = {
    &ARMMCRegisterClasses[QQQQPR_with_ssub_12RegClassID],
    QQQQPR_with_ssub_12SubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x0003FFFC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    QQQQPR_with_ssub_12Superclasses,
    QQQQPR_with_ssub_12GetRawAllocationOrder
  };

  extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[QQQQPR_with_dsub_0_in_DPR_8RegClassID],
    QQQQPR_with_dsub_0_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x0003FFFC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    QQQQPR_with_dsub_0_in_DPR_8Superclasses,
    QQQQPR_with_dsub_0_in_DPR_8GetRawAllocationOrder
  };

  extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[QQQQPR_with_dsub_2_in_DPR_8RegClassID],
    QQQQPR_with_dsub_2_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x0003FFFC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    QQQQPR_with_dsub_2_in_DPR_8Superclasses,
    QQQQPR_with_dsub_2_in_DPR_8GetRawAllocationOrder
  };

  extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[QQQQPR_with_dsub_4_in_DPR_8RegClassID],
    QQQQPR_with_dsub_4_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x0003FFFC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    QQQQPR_with_dsub_4_in_DPR_8Superclasses,
    QQQQPR_with_dsub_4_in_DPR_8GetRawAllocationOrder
  };

  extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass = {
    &ARMMCRegisterClasses[QQQQPR_with_dsub_6_in_DPR_8RegClassID],
    QQQQPR_with_dsub_6_in_DPR_8SubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x0003FFFC),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    QQQQPR_with_dsub_6_in_DPR_8Superclasses,
    QQQQPR_with_dsub_6_in_DPR_8GetRawAllocationOrder
  };

} // end namespace ARM

namespace {
  const TargetRegisterClass* const RegisterClasses[] = {
    &ARM::HPRRegClass,
    &ARM::SPRRegClass,
    &ARM::GPRRegClass,
    &ARM::GPRwithAPSRRegClass,
    &ARM::SPR_8RegClass,
    &ARM::GPRnopcRegClass,
    &ARM::rGPRRegClass,
    &ARM::tGPRwithpcRegClass,
    &ARM::hGPRRegClass,
    &ARM::tGPRRegClass,
    &ARM::GPRnopc_and_hGPRRegClass,
    &ARM::hGPR_and_rGPRRegClass,
    &ARM::tcGPRRegClass,
    &ARM::tGPR_and_tcGPRRegClass,
    &ARM::CCRRegClass,
    &ARM::GPRspRegClass,
    &ARM::hGPR_and_tGPRwithpcRegClass,
    &ARM::hGPR_and_tcGPRRegClass,
    &ARM::DPRRegClass,
    &ARM::DPR_VFP2RegClass,
    &ARM::DPR_8RegClass,
    &ARM::GPRPairRegClass,
    &ARM::GPRPair_with_gsub_1_in_rGPRRegClass,
    &ARM::GPRPair_with_gsub_0_in_tGPRRegClass,
    &ARM::GPRPair_with_gsub_0_in_hGPRRegClass,
    &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass,
    &ARM::GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClass,
    &ARM::GPRPair_with_gsub_1_in_tcGPRRegClass,
    &ARM::GPRPair_with_gsub_1_in_GPRspRegClass,
    &ARM::DPairSpcRegClass,
    &ARM::DPairSpc_with_ssub_0RegClass,
    &ARM::DPairSpc_with_ssub_4RegClass,
    &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass,
    &ARM::DPairSpc_with_dsub_2_in_DPR_8RegClass,
    &ARM::DPairRegClass,
    &ARM::DPair_with_ssub_0RegClass,
    &ARM::QPRRegClass,
    &ARM::DPair_with_ssub_2RegClass,
    &ARM::DPair_with_dsub_0_in_DPR_8RegClass,
    &ARM::QPR_VFP2RegClass,
    &ARM::DPair_with_dsub_1_in_DPR_8RegClass,
    &ARM::QPR_8RegClass,
    &ARM::DTripleRegClass,
    &ARM::DTripleSpcRegClass,
    &ARM::DTripleSpc_with_ssub_0RegClass,
    &ARM::DTriple_with_ssub_0RegClass,
    &ARM::DTriple_with_qsub_0_in_QPRRegClass,
    &ARM::DTriple_with_ssub_2RegClass,
    &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    &ARM::DTripleSpc_with_ssub_4RegClass,
    &ARM::DTriple_with_ssub_4RegClass,
    &ARM::DTripleSpc_with_ssub_8RegClass,
    &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass,
    &ARM::DTriple_with_dsub_0_in_DPR_8RegClass,
    &ARM::DTriple_with_qsub_0_in_QPR_VFP2RegClass,
    &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    &ARM::DTriple_with_dsub_1_in_DPR_8RegClass,
    &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
    &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClass,
    &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass,
    &ARM::DTriple_with_dsub_2_in_DPR_8RegClass,
    &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass,
    &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    &ARM::DTriple_with_qsub_0_in_QPR_8RegClass,
    &ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClass,
    &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass,
    &ARM::DQuadSpcRegClass,
    &ARM::DQuadSpc_with_ssub_0RegClass,
    &ARM::DQuadSpc_with_ssub_4RegClass,
    &ARM::DQuadSpc_with_ssub_8RegClass,
    &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass,
    &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass,
    &ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClass,
    &ARM::DQuadRegClass,
    &ARM::DQuad_with_ssub_0RegClass,
    &ARM::DQuad_with_ssub_2RegClass,
    &ARM::QQPRRegClass,
    &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    &ARM::DQuad_with_ssub_4RegClass,
    &ARM::DQuad_with_ssub_6RegClass,
    &ARM::DQuad_with_dsub_0_in_DPR_8RegClass,
    &ARM::DQuad_with_qsub_0_in_QPR_VFP2RegClass,
    &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    &ARM::DQuad_with_dsub_1_in_DPR_8RegClass,
    &ARM::DQuad_with_qsub_1_in_QPR_VFP2RegClass,
    &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClass,
    &ARM::DQuad_with_dsub_2_in_DPR_8RegClass,
    &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    &ARM::DQuad_with_dsub_3_in_DPR_8RegClass,
    &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    &ARM::DQuad_with_qsub_0_in_QPR_8RegClass,
    &ARM::DQuad_with_qsub_1_in_QPR_8RegClass,
    &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass,
    &ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass,
    &ARM::QQQQPRRegClass,
    &ARM::QQQQPR_with_ssub_0RegClass,
    &ARM::QQQQPR_with_ssub_4RegClass,
    &ARM::QQQQPR_with_ssub_8RegClass,
    &ARM::QQQQPR_with_ssub_12RegClass,
    &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass,
    &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass,
    &ARM::QQQQPR_with_dsub_4_in_DPR_8RegClass,
    &ARM::QQQQPR_with_dsub_6_in_DPR_8RegClass,
  };
} // end anonymous namespace

static const TargetRegisterInfoDesc ARMRegInfoDesc[] = { // Extra Descriptors
  { 0, false },
  { 0, false },
  { 0, true },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 1, true },
  { 1, true },
  { 1, true },
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 1, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 1, true },
  { 1, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
};
unsigned ARMGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t RowMap[56] = {
    0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 4, 0, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 5, 5, 5, 2, 
  };
  static const uint8_t Rows[8][56] = {
    { 1, 2, 3, 4, 5, 0, 7, 0, 0, 0, 0, 0, 13, 14, 0, 0, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 0, 0, 29, 30, 0, 0, 33, 34, 35, 36, 37, 38, 0, 0, 0, 0, 43, 0, 45, 0, 0, 0, 0, 0, 51, 0, 0, 0, 0, 0, },
    { 2, 3, 4, 5, 6, 0, 8, 0, 0, 0, 0, 0, 37, 49, 0, 0, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 0, 0, 31, 32, 0, 0, 35, 36, 43, 44, 14, 40, 0, 0, 0, 0, 46, 0, 48, 0, 0, 0, 0, 0, 53, 0, 0, 0, 0, 0, },
    { 3, 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 14, 15, 0, 0, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 0, 0, 0, 0, 0, 0, 43, 44, 46, 47, 49, 0, 0, 0, 0, 0, 51, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 49, 55, 0, 0, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 46, 47, 51, 52, 15, 0, 0, 0, 0, 0, 53, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 0, 15, 16, 0, 0, 25, 26, 27, 28, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 51, 52, 53, 54, 55, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 55, 0, 0, 0, 27, 28, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 53, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 7, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 30, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
  };

  --IdxA; assert(IdxA < 56);
  --IdxB; assert(IdxB < 56);
  return Rows[RowMap[IdxA]][IdxB];
}

  struct MaskRolOp {
    LaneBitmask Mask;
    uint8_t  RotateLeft;
  };
  static const MaskRolOp LaneMaskComposeSequences[] = {
    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    { LaneBitmask(0xFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
    { LaneBitmask(0xFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
    { LaneBitmask(0xFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
    { LaneBitmask(0xFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 },   // Sequence 12
    { LaneBitmask(0xFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 },   // Sequence 14
    { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 16
    { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 18
    { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 20
    { LaneBitmask(0xFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 22
    { LaneBitmask(0xFFFFFFFF),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 24
    { LaneBitmask(0xFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 26
    { LaneBitmask(0xFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 },   // Sequence 28
    { LaneBitmask(0xFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 },   // Sequence 30
    { LaneBitmask(0xFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 },   // Sequence 32
    { LaneBitmask(0xFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 }  // Sequence 34
  };
  static const MaskRolOp *const CompositeSequences[] = {
    &LaneMaskComposeSequences[0], // to dsub_0
    &LaneMaskComposeSequences[2], // to dsub_1
    &LaneMaskComposeSequences[4], // to dsub_2
    &LaneMaskComposeSequences[6], // to dsub_3
    &LaneMaskComposeSequences[8], // to dsub_4
    &LaneMaskComposeSequences[10], // to dsub_5
    &LaneMaskComposeSequences[12], // to dsub_6
    &LaneMaskComposeSequences[14], // to dsub_7
    &LaneMaskComposeSequences[0], // to gsub_0
    &LaneMaskComposeSequences[16], // to gsub_1
    &LaneMaskComposeSequences[0], // to qqsub_0
    &LaneMaskComposeSequences[8], // to qqsub_1
    &LaneMaskComposeSequences[0], // to qsub_0
    &LaneMaskComposeSequences[4], // to qsub_1
    &LaneMaskComposeSequences[8], // to qsub_2
    &LaneMaskComposeSequences[12], // to qsub_3
    &LaneMaskComposeSequences[2], // to ssub_0
    &LaneMaskComposeSequences[18], // to ssub_1
    &LaneMaskComposeSequences[4], // to ssub_2
    &LaneMaskComposeSequences[20], // to ssub_3
    &LaneMaskComposeSequences[6], // to ssub_4
    &LaneMaskComposeSequences[22], // to ssub_5
    &LaneMaskComposeSequences[8], // to ssub_6
    &LaneMaskComposeSequences[24], // to ssub_7
    &LaneMaskComposeSequences[10], // to ssub_8
    &LaneMaskComposeSequences[26], // to ssub_9
    &LaneMaskComposeSequences[12], // to ssub_10
    &LaneMaskComposeSequences[28], // to ssub_11
    &LaneMaskComposeSequences[14], // to ssub_12
    &LaneMaskComposeSequences[30], // to ssub_13
    &LaneMaskComposeSequences[32], // to dsub_7_then_ssub_0
    &LaneMaskComposeSequences[34], // to dsub_7_then_ssub_1
    &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5
    &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7
    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5
    &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
    &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
    &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_8_ssub_9
    &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
    &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_dsub_5
    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_dsub_5_dsub_7
    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9
    &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    &LaneMaskComposeSequences[8], // to ssub_8_ssub_9_ssub_12_ssub_13
    &LaneMaskComposeSequences[8], // to ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
    &LaneMaskComposeSequences[10], // to dsub_5_dsub_7
    &LaneMaskComposeSequences[10], // to dsub_5_ssub_12_ssub_13_dsub_7
    &LaneMaskComposeSequences[10], // to dsub_5_ssub_12_ssub_13
    &LaneMaskComposeSequences[4] // to ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
  };

LaneBitmask ARMGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
  --IdxA; assert(IdxA < 56 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

LaneBitmask ARMGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
  LaneMask &= getSubRegIndexLaneMask(IdxA);
  --IdxA; assert(IdxA < 56 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

const TargetRegisterClass *ARMGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[103][56] = {
    {	// HPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// SPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// GPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// GPRwithAPSR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// SPR_8
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// GPRnopc
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// rGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// tGPRwithpc
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// hGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// tGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// GPRnopc_and_hGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// hGPR_and_rGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// tcGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// tGPR_and_tcGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// CCR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// GPRsp
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// hGPR_and_tGPRwithpc
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// hGPR_and_tcGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      20,	// ssub_0 -> DPR_VFP2
      20,	// ssub_1 -> DPR_VFP2
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DPR_VFP2
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      20,	// ssub_0 -> DPR_VFP2
      20,	// ssub_1 -> DPR_VFP2
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DPR_8
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      21,	// ssub_0 -> DPR_8
      21,	// ssub_1 -> DPR_8
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// GPRPair
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      22,	// gsub_0 -> GPRPair
      22,	// gsub_1 -> GPRPair
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// GPRPair_with_gsub_1_in_rGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      23,	// gsub_0 -> GPRPair_with_gsub_1_in_rGPR
      23,	// gsub_1 -> GPRPair_with_gsub_1_in_rGPR
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// GPRPair_with_gsub_0_in_tGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      24,	// gsub_0 -> GPRPair_with_gsub_0_in_tGPR
      24,	// gsub_1 -> GPRPair_with_gsub_0_in_tGPR
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// GPRPair_with_gsub_0_in_hGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      25,	// gsub_0 -> GPRPair_with_gsub_0_in_hGPR
      25,	// gsub_1 -> GPRPair_with_gsub_0_in_hGPR
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// GPRPair_with_gsub_0_in_tcGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      26,	// gsub_0 -> GPRPair_with_gsub_0_in_tcGPR
      26,	// gsub_1 -> GPRPair_with_gsub_0_in_tcGPR
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// GPRPair_with_gsub_1_in_hGPR_and_rGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      27,	// gsub_0 -> GPRPair_with_gsub_1_in_hGPR_and_rGPR
      27,	// gsub_1 -> GPRPair_with_gsub_1_in_hGPR_and_rGPR
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// GPRPair_with_gsub_1_in_tcGPR
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      28,	// gsub_0 -> GPRPair_with_gsub_1_in_tcGPR
      28,	// gsub_1 -> GPRPair_with_gsub_1_in_tcGPR
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// GPRPair_with_gsub_1_in_GPRsp
      0,	// dsub_0
      0,	// dsub_1
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      29,	// gsub_0 -> GPRPair_with_gsub_1_in_GPRsp
      29,	// gsub_1 -> GPRPair_with_gsub_1_in_GPRsp
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      0,	// ssub_0
      0,	// ssub_1
      0,	// ssub_2
      0,	// ssub_3
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DPairSpc
      30,	// dsub_0 -> DPairSpc
      0,	// dsub_1
      30,	// dsub_2 -> DPairSpc
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      31,	// ssub_0 -> DPairSpc_with_ssub_0
      31,	// ssub_1 -> DPairSpc_with_ssub_0
      0,	// ssub_2
      0,	// ssub_3
      32,	// ssub_4 -> DPairSpc_with_ssub_4
      32,	// ssub_5 -> DPairSpc_with_ssub_4
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DPairSpc_with_ssub_0
      31,	// dsub_0 -> DPairSpc_with_ssub_0
      0,	// dsub_1
      31,	// dsub_2 -> DPairSpc_with_ssub_0
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      31,	// ssub_0 -> DPairSpc_with_ssub_0
      31,	// ssub_1 -> DPairSpc_with_ssub_0
      0,	// ssub_2
      0,	// ssub_3
      32,	// ssub_4 -> DPairSpc_with_ssub_4
      32,	// ssub_5 -> DPairSpc_with_ssub_4
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DPairSpc_with_ssub_4
      32,	// dsub_0 -> DPairSpc_with_ssub_4
      0,	// dsub_1
      32,	// dsub_2 -> DPairSpc_with_ssub_4
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      32,	// ssub_0 -> DPairSpc_with_ssub_4
      32,	// ssub_1 -> DPairSpc_with_ssub_4
      0,	// ssub_2
      0,	// ssub_3
      32,	// ssub_4 -> DPairSpc_with_ssub_4
      32,	// ssub_5 -> DPairSpc_with_ssub_4
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DPairSpc_with_dsub_0_in_DPR_8
      33,	// dsub_0 -> DPairSpc_with_dsub_0_in_DPR_8
      0,	// dsub_1
      33,	// dsub_2 -> DPairSpc_with_dsub_0_in_DPR_8
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      33,	// ssub_0 -> DPairSpc_with_dsub_0_in_DPR_8
      33,	// ssub_1 -> DPairSpc_with_dsub_0_in_DPR_8
      0,	// ssub_2
      0,	// ssub_3
      33,	// ssub_4 -> DPairSpc_with_dsub_0_in_DPR_8
      33,	// ssub_5 -> DPairSpc_with_dsub_0_in_DPR_8
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DPairSpc_with_dsub_2_in_DPR_8
      34,	// dsub_0 -> DPairSpc_with_dsub_2_in_DPR_8
      0,	// dsub_1
      34,	// dsub_2 -> DPairSpc_with_dsub_2_in_DPR_8
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      34,	// ssub_0 -> DPairSpc_with_dsub_2_in_DPR_8
      34,	// ssub_1 -> DPairSpc_with_dsub_2_in_DPR_8
      0,	// ssub_2
      0,	// ssub_3
      34,	// ssub_4 -> DPairSpc_with_dsub_2_in_DPR_8
      34,	// ssub_5 -> DPairSpc_with_dsub_2_in_DPR_8
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DPair
      35,	// dsub_0 -> DPair
      35,	// dsub_1 -> DPair
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      36,	// ssub_0 -> DPair_with_ssub_0
      36,	// ssub_1 -> DPair_with_ssub_0
      38,	// ssub_2 -> DPair_with_ssub_2
      38,	// ssub_3 -> DPair_with_ssub_2
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DPair_with_ssub_0
      36,	// dsub_0 -> DPair_with_ssub_0
      36,	// dsub_1 -> DPair_with_ssub_0
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      36,	// ssub_0 -> DPair_with_ssub_0
      36,	// ssub_1 -> DPair_with_ssub_0
      38,	// ssub_2 -> DPair_with_ssub_2
      38,	// ssub_3 -> DPair_with_ssub_2
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// QPR
      37,	// dsub_0 -> QPR
      37,	// dsub_1 -> QPR
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      40,	// ssub_0 -> QPR_VFP2
      40,	// ssub_1 -> QPR_VFP2
      40,	// ssub_2 -> QPR_VFP2
      40,	// ssub_3 -> QPR_VFP2
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DPair_with_ssub_2
      38,	// dsub_0 -> DPair_with_ssub_2
      38,	// dsub_1 -> DPair_with_ssub_2
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      38,	// ssub_0 -> DPair_with_ssub_2
      38,	// ssub_1 -> DPair_with_ssub_2
      38,	// ssub_2 -> DPair_with_ssub_2
      38,	// ssub_3 -> DPair_with_ssub_2
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DPair_with_dsub_0_in_DPR_8
      39,	// dsub_0 -> DPair_with_dsub_0_in_DPR_8
      39,	// dsub_1 -> DPair_with_dsub_0_in_DPR_8
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      39,	// ssub_0 -> DPair_with_dsub_0_in_DPR_8
      39,	// ssub_1 -> DPair_with_dsub_0_in_DPR_8
      39,	// ssub_2 -> DPair_with_dsub_0_in_DPR_8
      39,	// ssub_3 -> DPair_with_dsub_0_in_DPR_8
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// QPR_VFP2
      40,	// dsub_0 -> QPR_VFP2
      40,	// dsub_1 -> QPR_VFP2
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      40,	// ssub_0 -> QPR_VFP2
      40,	// ssub_1 -> QPR_VFP2
      40,	// ssub_2 -> QPR_VFP2
      40,	// ssub_3 -> QPR_VFP2
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DPair_with_dsub_1_in_DPR_8
      41,	// dsub_0 -> DPair_with_dsub_1_in_DPR_8
      41,	// dsub_1 -> DPair_with_dsub_1_in_DPR_8
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      41,	// ssub_0 -> DPair_with_dsub_1_in_DPR_8
      41,	// ssub_1 -> DPair_with_dsub_1_in_DPR_8
      41,	// ssub_2 -> DPair_with_dsub_1_in_DPR_8
      41,	// ssub_3 -> DPair_with_dsub_1_in_DPR_8
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// QPR_8
      42,	// dsub_0 -> QPR_8
      42,	// dsub_1 -> QPR_8
      0,	// dsub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      42,	// ssub_0 -> QPR_8
      42,	// ssub_1 -> QPR_8
      42,	// ssub_2 -> QPR_8
      42,	// ssub_3 -> QPR_8
      0,	// ssub_4
      0,	// ssub_5
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      0,	// ssub_0_ssub_1_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple
      43,	// dsub_0 -> DTriple
      43,	// dsub_1 -> DTriple
      43,	// dsub_2 -> DTriple
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      43,	// qsub_0 -> DTriple
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      46,	// ssub_0 -> DTriple_with_ssub_0
      46,	// ssub_1 -> DTriple_with_ssub_0
      48,	// ssub_2 -> DTriple_with_ssub_2
      48,	// ssub_3 -> DTriple_with_ssub_2
      51,	// ssub_4 -> DTriple_with_ssub_4
      51,	// ssub_5 -> DTriple_with_ssub_4
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      43,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      43,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTripleSpc
      44,	// dsub_0 -> DTripleSpc
      0,	// dsub_1
      44,	// dsub_2 -> DTripleSpc
      0,	// dsub_3
      44,	// dsub_4 -> DTripleSpc
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      45,	// ssub_0 -> DTripleSpc_with_ssub_0
      45,	// ssub_1 -> DTripleSpc_with_ssub_0
      0,	// ssub_2
      0,	// ssub_3
      50,	// ssub_4 -> DTripleSpc_with_ssub_4
      50,	// ssub_5 -> DTripleSpc_with_ssub_4
      0,	// ssub_6
      0,	// ssub_7
      52,	// ssub_8 -> DTripleSpc_with_ssub_8
      52,	// ssub_9 -> DTripleSpc_with_ssub_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      44,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      44,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTripleSpc_with_ssub_0
      45,	// dsub_0 -> DTripleSpc_with_ssub_0
      0,	// dsub_1
      45,	// dsub_2 -> DTripleSpc_with_ssub_0
      0,	// dsub_3
      45,	// dsub_4 -> DTripleSpc_with_ssub_0
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      45,	// ssub_0 -> DTripleSpc_with_ssub_0
      45,	// ssub_1 -> DTripleSpc_with_ssub_0
      0,	// ssub_2
      0,	// ssub_3
      50,	// ssub_4 -> DTripleSpc_with_ssub_4
      50,	// ssub_5 -> DTripleSpc_with_ssub_4
      0,	// ssub_6
      0,	// ssub_7
      52,	// ssub_8 -> DTripleSpc_with_ssub_8
      52,	// ssub_9 -> DTripleSpc_with_ssub_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      45,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_0
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      45,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_0
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_ssub_0
      46,	// dsub_0 -> DTriple_with_ssub_0
      46,	// dsub_1 -> DTriple_with_ssub_0
      46,	// dsub_2 -> DTriple_with_ssub_0
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      46,	// qsub_0 -> DTriple_with_ssub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      46,	// ssub_0 -> DTriple_with_ssub_0
      46,	// ssub_1 -> DTriple_with_ssub_0
      48,	// ssub_2 -> DTriple_with_ssub_2
      48,	// ssub_3 -> DTriple_with_ssub_2
      51,	// ssub_4 -> DTriple_with_ssub_4
      51,	// ssub_5 -> DTriple_with_ssub_4
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      46,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_0
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      46,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_0
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_qsub_0_in_QPR
      47,	// dsub_0 -> DTriple_with_qsub_0_in_QPR
      47,	// dsub_1 -> DTriple_with_qsub_0_in_QPR
      47,	// dsub_2 -> DTriple_with_qsub_0_in_QPR
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      47,	// qsub_0 -> DTriple_with_qsub_0_in_QPR
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      55,	// ssub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
      55,	// ssub_1 -> DTriple_with_qsub_0_in_QPR_VFP2
      55,	// ssub_2 -> DTriple_with_qsub_0_in_QPR_VFP2
      55,	// ssub_3 -> DTriple_with_qsub_0_in_QPR_VFP2
      59,	// ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      59,	// ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      47,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      47,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_ssub_2
      48,	// dsub_0 -> DTriple_with_ssub_2
      48,	// dsub_1 -> DTriple_with_ssub_2
      48,	// dsub_2 -> DTriple_with_ssub_2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      48,	// qsub_0 -> DTriple_with_ssub_2
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      48,	// ssub_0 -> DTriple_with_ssub_2
      48,	// ssub_1 -> DTriple_with_ssub_2
      48,	// ssub_2 -> DTriple_with_ssub_2
      48,	// ssub_3 -> DTriple_with_ssub_2
      51,	// ssub_4 -> DTriple_with_ssub_4
      51,	// ssub_5 -> DTriple_with_ssub_4
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      48,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      48,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      49,	// dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      49,	// dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      49,	// dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      49,	// qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      56,	// ssub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      56,	// ssub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      58,	// ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      49,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      49,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTripleSpc_with_ssub_4
      50,	// dsub_0 -> DTripleSpc_with_ssub_4
      0,	// dsub_1
      50,	// dsub_2 -> DTripleSpc_with_ssub_4
      0,	// dsub_3
      50,	// dsub_4 -> DTripleSpc_with_ssub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      50,	// ssub_0 -> DTripleSpc_with_ssub_4
      50,	// ssub_1 -> DTripleSpc_with_ssub_4
      0,	// ssub_2
      0,	// ssub_3
      50,	// ssub_4 -> DTripleSpc_with_ssub_4
      50,	// ssub_5 -> DTripleSpc_with_ssub_4
      0,	// ssub_6
      0,	// ssub_7
      52,	// ssub_8 -> DTripleSpc_with_ssub_8
      52,	// ssub_9 -> DTripleSpc_with_ssub_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      50,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_4
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      50,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_4
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_ssub_4
      51,	// dsub_0 -> DTriple_with_ssub_4
      51,	// dsub_1 -> DTriple_with_ssub_4
      51,	// dsub_2 -> DTriple_with_ssub_4
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      51,	// qsub_0 -> DTriple_with_ssub_4
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      51,	// ssub_0 -> DTriple_with_ssub_4
      51,	// ssub_1 -> DTriple_with_ssub_4
      51,	// ssub_2 -> DTriple_with_ssub_4
      51,	// ssub_3 -> DTriple_with_ssub_4
      51,	// ssub_4 -> DTriple_with_ssub_4
      51,	// ssub_5 -> DTriple_with_ssub_4
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      51,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_4
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      51,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_4
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTripleSpc_with_ssub_8
      52,	// dsub_0 -> DTripleSpc_with_ssub_8
      0,	// dsub_1
      52,	// dsub_2 -> DTripleSpc_with_ssub_8
      0,	// dsub_3
      52,	// dsub_4 -> DTripleSpc_with_ssub_8
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      52,	// ssub_0 -> DTripleSpc_with_ssub_8
      52,	// ssub_1 -> DTripleSpc_with_ssub_8
      0,	// ssub_2
      0,	// ssub_3
      52,	// ssub_4 -> DTripleSpc_with_ssub_8
      52,	// ssub_5 -> DTripleSpc_with_ssub_8
      0,	// ssub_6
      0,	// ssub_7
      52,	// ssub_8 -> DTripleSpc_with_ssub_8
      52,	// ssub_9 -> DTripleSpc_with_ssub_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      52,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_8
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      52,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_8
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTripleSpc_with_dsub_0_in_DPR_8
      53,	// dsub_0 -> DTripleSpc_with_dsub_0_in_DPR_8
      0,	// dsub_1
      53,	// dsub_2 -> DTripleSpc_with_dsub_0_in_DPR_8
      0,	// dsub_3
      53,	// dsub_4 -> DTripleSpc_with_dsub_0_in_DPR_8
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      53,	// ssub_0 -> DTripleSpc_with_dsub_0_in_DPR_8
      53,	// ssub_1 -> DTripleSpc_with_dsub_0_in_DPR_8
      0,	// ssub_2
      0,	// ssub_3
      53,	// ssub_4 -> DTripleSpc_with_dsub_0_in_DPR_8
      53,	// ssub_5 -> DTripleSpc_with_dsub_0_in_DPR_8
      0,	// ssub_6
      0,	// ssub_7
      53,	// ssub_8 -> DTripleSpc_with_dsub_0_in_DPR_8
      53,	// ssub_9 -> DTripleSpc_with_dsub_0_in_DPR_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      53,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_0_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      53,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_0_in_DPR_8
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_dsub_0_in_DPR_8
      54,	// dsub_0 -> DTriple_with_dsub_0_in_DPR_8
      54,	// dsub_1 -> DTriple_with_dsub_0_in_DPR_8
      54,	// dsub_2 -> DTriple_with_dsub_0_in_DPR_8
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      54,	// qsub_0 -> DTriple_with_dsub_0_in_DPR_8
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      54,	// ssub_0 -> DTriple_with_dsub_0_in_DPR_8
      54,	// ssub_1 -> DTriple_with_dsub_0_in_DPR_8
      54,	// ssub_2 -> DTriple_with_dsub_0_in_DPR_8
      54,	// ssub_3 -> DTriple_with_dsub_0_in_DPR_8
      54,	// ssub_4 -> DTriple_with_dsub_0_in_DPR_8
      54,	// ssub_5 -> DTriple_with_dsub_0_in_DPR_8
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      54,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      54,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_qsub_0_in_QPR_VFP2
      55,	// dsub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
      55,	// dsub_1 -> DTriple_with_qsub_0_in_QPR_VFP2
      55,	// dsub_2 -> DTriple_with_qsub_0_in_QPR_VFP2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      55,	// qsub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      55,	// ssub_0 -> DTriple_with_qsub_0_in_QPR_VFP2
      55,	// ssub_1 -> DTriple_with_qsub_0_in_QPR_VFP2
      55,	// ssub_2 -> DTriple_with_qsub_0_in_QPR_VFP2
      55,	// ssub_3 -> DTriple_with_qsub_0_in_QPR_VFP2
      59,	// ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      59,	// ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      55,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_VFP2
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      55,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_VFP2
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      56,	// dsub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      56,	// dsub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      56,	// dsub_2 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      56,	// qsub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      56,	// ssub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      56,	// ssub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      58,	// ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      56,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      56,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_dsub_1_in_DPR_8
      57,	// dsub_0 -> DTriple_with_dsub_1_in_DPR_8
      57,	// dsub_1 -> DTriple_with_dsub_1_in_DPR_8
      57,	// dsub_2 -> DTriple_with_dsub_1_in_DPR_8
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      57,	// qsub_0 -> DTriple_with_dsub_1_in_DPR_8
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      57,	// ssub_0 -> DTriple_with_dsub_1_in_DPR_8
      57,	// ssub_1 -> DTriple_with_dsub_1_in_DPR_8
      57,	// ssub_2 -> DTriple_with_dsub_1_in_DPR_8
      57,	// ssub_3 -> DTriple_with_dsub_1_in_DPR_8
      57,	// ssub_4 -> DTriple_with_dsub_1_in_DPR_8
      57,	// ssub_5 -> DTriple_with_dsub_1_in_DPR_8
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      57,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_1_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      57,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_1_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      58,	// qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      58,	// ssub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// ssub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      58,	// ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      58,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      58,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      59,	// dsub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      59,	// dsub_1 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      59,	// dsub_2 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      59,	// qsub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      59,	// ssub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      59,	// ssub_1 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      59,	// ssub_2 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      59,	// ssub_3 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      59,	// ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      59,	// ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      59,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      59,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTripleSpc_with_dsub_2_in_DPR_8
      60,	// dsub_0 -> DTripleSpc_with_dsub_2_in_DPR_8
      0,	// dsub_1
      60,	// dsub_2 -> DTripleSpc_with_dsub_2_in_DPR_8
      0,	// dsub_3
      60,	// dsub_4 -> DTripleSpc_with_dsub_2_in_DPR_8
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      60,	// ssub_0 -> DTripleSpc_with_dsub_2_in_DPR_8
      60,	// ssub_1 -> DTripleSpc_with_dsub_2_in_DPR_8
      0,	// ssub_2
      0,	// ssub_3
      60,	// ssub_4 -> DTripleSpc_with_dsub_2_in_DPR_8
      60,	// ssub_5 -> DTripleSpc_with_dsub_2_in_DPR_8
      0,	// ssub_6
      0,	// ssub_7
      60,	// ssub_8 -> DTripleSpc_with_dsub_2_in_DPR_8
      60,	// ssub_9 -> DTripleSpc_with_dsub_2_in_DPR_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      60,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_2_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      60,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_2_in_DPR_8
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_dsub_2_in_DPR_8
      61,	// dsub_0 -> DTriple_with_dsub_2_in_DPR_8
      61,	// dsub_1 -> DTriple_with_dsub_2_in_DPR_8
      61,	// dsub_2 -> DTriple_with_dsub_2_in_DPR_8
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      61,	// qsub_0 -> DTriple_with_dsub_2_in_DPR_8
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      61,	// ssub_0 -> DTriple_with_dsub_2_in_DPR_8
      61,	// ssub_1 -> DTriple_with_dsub_2_in_DPR_8
      61,	// ssub_2 -> DTriple_with_dsub_2_in_DPR_8
      61,	// ssub_3 -> DTriple_with_dsub_2_in_DPR_8
      61,	// ssub_4 -> DTriple_with_dsub_2_in_DPR_8
      61,	// ssub_5 -> DTriple_with_dsub_2_in_DPR_8
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      61,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      61,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTripleSpc_with_dsub_4_in_DPR_8
      62,	// dsub_0 -> DTripleSpc_with_dsub_4_in_DPR_8
      0,	// dsub_1
      62,	// dsub_2 -> DTripleSpc_with_dsub_4_in_DPR_8
      0,	// dsub_3
      62,	// dsub_4 -> DTripleSpc_with_dsub_4_in_DPR_8
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      62,	// ssub_0 -> DTripleSpc_with_dsub_4_in_DPR_8
      62,	// ssub_1 -> DTripleSpc_with_dsub_4_in_DPR_8
      0,	// ssub_2
      0,	// ssub_3
      62,	// ssub_4 -> DTripleSpc_with_dsub_4_in_DPR_8
      62,	// ssub_5 -> DTripleSpc_with_dsub_4_in_DPR_8
      0,	// ssub_6
      0,	// ssub_7
      62,	// ssub_8 -> DTripleSpc_with_dsub_4_in_DPR_8
      62,	// ssub_9 -> DTripleSpc_with_dsub_4_in_DPR_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      62,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_4_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      62,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_4_in_DPR_8
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      63,	// dsub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      63,	// dsub_1 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      63,	// dsub_2 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      63,	// qsub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      63,	// ssub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      63,	// ssub_1 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      63,	// ssub_2 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      63,	// ssub_3 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      63,	// ssub_4 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      63,	// ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      63,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      63,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_qsub_0_in_QPR_8
      64,	// dsub_0 -> DTriple_with_qsub_0_in_QPR_8
      64,	// dsub_1 -> DTriple_with_qsub_0_in_QPR_8
      64,	// dsub_2 -> DTriple_with_qsub_0_in_QPR_8
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      64,	// qsub_0 -> DTriple_with_qsub_0_in_QPR_8
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      64,	// ssub_0 -> DTriple_with_qsub_0_in_QPR_8
      64,	// ssub_1 -> DTriple_with_qsub_0_in_QPR_8
      64,	// ssub_2 -> DTriple_with_qsub_0_in_QPR_8
      64,	// ssub_3 -> DTriple_with_qsub_0_in_QPR_8
      64,	// ssub_4 -> DTriple_with_qsub_0_in_QPR_8
      64,	// ssub_5 -> DTriple_with_qsub_0_in_QPR_8
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      64,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_8
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      64,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_8
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
      65,	// dsub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
      65,	// dsub_1 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
      65,	// dsub_2 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      65,	// qsub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      65,	// ssub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
      65,	// ssub_1 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
      65,	// ssub_2 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
      65,	// ssub_3 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
      65,	// ssub_4 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
      65,	// ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      65,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      65,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      66,	// dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      66,	// dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      66,	// dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      0,	// dsub_3
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      66,	// qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      66,	// ssub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      66,	// ssub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      66,	// ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      66,	// ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      66,	// ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      66,	// ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      0,	// ssub_6
      0,	// ssub_7
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      66,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      66,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuadSpc
      67,	// dsub_0 -> DQuadSpc
      0,	// dsub_1
      67,	// dsub_2 -> DQuadSpc
      0,	// dsub_3
      67,	// dsub_4 -> DQuadSpc
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      68,	// ssub_0 -> DQuadSpc_with_ssub_0
      68,	// ssub_1 -> DQuadSpc_with_ssub_0
      0,	// ssub_2
      0,	// ssub_3
      69,	// ssub_4 -> DQuadSpc_with_ssub_4
      69,	// ssub_5 -> DQuadSpc_with_ssub_4
      0,	// ssub_6
      0,	// ssub_7
      70,	// ssub_8 -> DQuadSpc_with_ssub_8
      70,	// ssub_9 -> DQuadSpc_with_ssub_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      67,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      67,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuadSpc_with_ssub_0
      68,	// dsub_0 -> DQuadSpc_with_ssub_0
      0,	// dsub_1
      68,	// dsub_2 -> DQuadSpc_with_ssub_0
      0,	// dsub_3
      68,	// dsub_4 -> DQuadSpc_with_ssub_0
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      68,	// ssub_0 -> DQuadSpc_with_ssub_0
      68,	// ssub_1 -> DQuadSpc_with_ssub_0
      0,	// ssub_2
      0,	// ssub_3
      69,	// ssub_4 -> DQuadSpc_with_ssub_4
      69,	// ssub_5 -> DQuadSpc_with_ssub_4
      0,	// ssub_6
      0,	// ssub_7
      70,	// ssub_8 -> DQuadSpc_with_ssub_8
      70,	// ssub_9 -> DQuadSpc_with_ssub_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      68,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_0
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      68,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_0
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuadSpc_with_ssub_4
      69,	// dsub_0 -> DQuadSpc_with_ssub_4
      0,	// dsub_1
      69,	// dsub_2 -> DQuadSpc_with_ssub_4
      0,	// dsub_3
      69,	// dsub_4 -> DQuadSpc_with_ssub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      69,	// ssub_0 -> DQuadSpc_with_ssub_4
      69,	// ssub_1 -> DQuadSpc_with_ssub_4
      0,	// ssub_2
      0,	// ssub_3
      69,	// ssub_4 -> DQuadSpc_with_ssub_4
      69,	// ssub_5 -> DQuadSpc_with_ssub_4
      0,	// ssub_6
      0,	// ssub_7
      70,	// ssub_8 -> DQuadSpc_with_ssub_8
      70,	// ssub_9 -> DQuadSpc_with_ssub_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      69,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_4
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      69,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_4
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuadSpc_with_ssub_8
      70,	// dsub_0 -> DQuadSpc_with_ssub_8
      0,	// dsub_1
      70,	// dsub_2 -> DQuadSpc_with_ssub_8
      0,	// dsub_3
      70,	// dsub_4 -> DQuadSpc_with_ssub_8
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      70,	// ssub_0 -> DQuadSpc_with_ssub_8
      70,	// ssub_1 -> DQuadSpc_with_ssub_8
      0,	// ssub_2
      0,	// ssub_3
      70,	// ssub_4 -> DQuadSpc_with_ssub_8
      70,	// ssub_5 -> DQuadSpc_with_ssub_8
      0,	// ssub_6
      0,	// ssub_7
      70,	// ssub_8 -> DQuadSpc_with_ssub_8
      70,	// ssub_9 -> DQuadSpc_with_ssub_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      70,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_8
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      70,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_8
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuadSpc_with_dsub_0_in_DPR_8
      71,	// dsub_0 -> DQuadSpc_with_dsub_0_in_DPR_8
      0,	// dsub_1
      71,	// dsub_2 -> DQuadSpc_with_dsub_0_in_DPR_8
      0,	// dsub_3
      71,	// dsub_4 -> DQuadSpc_with_dsub_0_in_DPR_8
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      71,	// ssub_0 -> DQuadSpc_with_dsub_0_in_DPR_8
      71,	// ssub_1 -> DQuadSpc_with_dsub_0_in_DPR_8
      0,	// ssub_2
      0,	// ssub_3
      71,	// ssub_4 -> DQuadSpc_with_dsub_0_in_DPR_8
      71,	// ssub_5 -> DQuadSpc_with_dsub_0_in_DPR_8
      0,	// ssub_6
      0,	// ssub_7
      71,	// ssub_8 -> DQuadSpc_with_dsub_0_in_DPR_8
      71,	// ssub_9 -> DQuadSpc_with_dsub_0_in_DPR_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      71,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_0_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      71,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_0_in_DPR_8
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuadSpc_with_dsub_2_in_DPR_8
      72,	// dsub_0 -> DQuadSpc_with_dsub_2_in_DPR_8
      0,	// dsub_1
      72,	// dsub_2 -> DQuadSpc_with_dsub_2_in_DPR_8
      0,	// dsub_3
      72,	// dsub_4 -> DQuadSpc_with_dsub_2_in_DPR_8
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      72,	// ssub_0 -> DQuadSpc_with_dsub_2_in_DPR_8
      72,	// ssub_1 -> DQuadSpc_with_dsub_2_in_DPR_8
      0,	// ssub_2
      0,	// ssub_3
      72,	// ssub_4 -> DQuadSpc_with_dsub_2_in_DPR_8
      72,	// ssub_5 -> DQuadSpc_with_dsub_2_in_DPR_8
      0,	// ssub_6
      0,	// ssub_7
      72,	// ssub_8 -> DQuadSpc_with_dsub_2_in_DPR_8
      72,	// ssub_9 -> DQuadSpc_with_dsub_2_in_DPR_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      72,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_2_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      72,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_2_in_DPR_8
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuadSpc_with_dsub_4_in_DPR_8
      73,	// dsub_0 -> DQuadSpc_with_dsub_4_in_DPR_8
      0,	// dsub_1
      73,	// dsub_2 -> DQuadSpc_with_dsub_4_in_DPR_8
      0,	// dsub_3
      73,	// dsub_4 -> DQuadSpc_with_dsub_4_in_DPR_8
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      0,	// qsub_0
      0,	// qsub_1
      0,	// qsub_2
      0,	// qsub_3
      73,	// ssub_0 -> DQuadSpc_with_dsub_4_in_DPR_8
      73,	// ssub_1 -> DQuadSpc_with_dsub_4_in_DPR_8
      0,	// ssub_2
      0,	// ssub_3
      73,	// ssub_4 -> DQuadSpc_with_dsub_4_in_DPR_8
      73,	// ssub_5 -> DQuadSpc_with_dsub_4_in_DPR_8
      0,	// ssub_6
      0,	// ssub_7
      73,	// ssub_8 -> DQuadSpc_with_dsub_4_in_DPR_8
      73,	// ssub_9 -> DQuadSpc_with_dsub_4_in_DPR_8
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      73,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_4_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      73,	// ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_4_in_DPR_8
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad
      74,	// dsub_0 -> DQuad
      74,	// dsub_1 -> DQuad
      74,	// dsub_2 -> DQuad
      74,	// dsub_3 -> DQuad
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      74,	// qsub_0 -> DQuad
      74,	// qsub_1 -> DQuad
      0,	// qsub_2
      0,	// qsub_3
      75,	// ssub_0 -> DQuad_with_ssub_0
      75,	// ssub_1 -> DQuad_with_ssub_0
      76,	// ssub_2 -> DQuad_with_ssub_2
      76,	// ssub_3 -> DQuad_with_ssub_2
      79,	// ssub_4 -> DQuad_with_ssub_4
      79,	// ssub_5 -> DQuad_with_ssub_4
      80,	// ssub_6 -> DQuad_with_ssub_6
      80,	// ssub_7 -> DQuad_with_ssub_6
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      74,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad
      74,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad
      74,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad
      74,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad
      74,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_ssub_0
      75,	// dsub_0 -> DQuad_with_ssub_0
      75,	// dsub_1 -> DQuad_with_ssub_0
      75,	// dsub_2 -> DQuad_with_ssub_0
      75,	// dsub_3 -> DQuad_with_ssub_0
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      75,	// qsub_0 -> DQuad_with_ssub_0
      75,	// qsub_1 -> DQuad_with_ssub_0
      0,	// qsub_2
      0,	// qsub_3
      75,	// ssub_0 -> DQuad_with_ssub_0
      75,	// ssub_1 -> DQuad_with_ssub_0
      76,	// ssub_2 -> DQuad_with_ssub_2
      76,	// ssub_3 -> DQuad_with_ssub_2
      79,	// ssub_4 -> DQuad_with_ssub_4
      79,	// ssub_5 -> DQuad_with_ssub_4
      80,	// ssub_6 -> DQuad_with_ssub_6
      80,	// ssub_7 -> DQuad_with_ssub_6
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      75,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_0
      75,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0
      75,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_0
      75,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_0
      75,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_ssub_2
      76,	// dsub_0 -> DQuad_with_ssub_2
      76,	// dsub_1 -> DQuad_with_ssub_2
      76,	// dsub_2 -> DQuad_with_ssub_2
      76,	// dsub_3 -> DQuad_with_ssub_2
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      76,	// qsub_0 -> DQuad_with_ssub_2
      76,	// qsub_1 -> DQuad_with_ssub_2
      0,	// qsub_2
      0,	// qsub_3
      76,	// ssub_0 -> DQuad_with_ssub_2
      76,	// ssub_1 -> DQuad_with_ssub_2
      76,	// ssub_2 -> DQuad_with_ssub_2
      76,	// ssub_3 -> DQuad_with_ssub_2
      79,	// ssub_4 -> DQuad_with_ssub_4
      79,	// ssub_5 -> DQuad_with_ssub_4
      80,	// ssub_6 -> DQuad_with_ssub_6
      80,	// ssub_7 -> DQuad_with_ssub_6
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      76,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2
      76,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2
      76,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2
      76,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2
      76,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// QQPR
      77,	// dsub_0 -> QQPR
      77,	// dsub_1 -> QQPR
      77,	// dsub_2 -> QQPR
      77,	// dsub_3 -> QQPR
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      77,	// qsub_0 -> QQPR
      77,	// qsub_1 -> QQPR
      0,	// qsub_2
      0,	// qsub_3
      82,	// ssub_0 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// ssub_1 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// ssub_2 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// ssub_3 -> DQuad_with_qsub_0_in_QPR_VFP2
      85,	// ssub_4 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_6 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      77,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQPR
      77,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQPR
      77,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQPR
      77,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQPR
      77,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQPR
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      78,	// dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      78,	// dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      78,	// dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      78,	// dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      78,	// qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      78,	// qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// qsub_2
      0,	// qsub_3
      83,	// ssub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      83,	// ssub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      86,	// ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      88,	// ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      78,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      78,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      78,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      78,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      78,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_ssub_4
      79,	// dsub_0 -> DQuad_with_ssub_4
      79,	// dsub_1 -> DQuad_with_ssub_4
      79,	// dsub_2 -> DQuad_with_ssub_4
      79,	// dsub_3 -> DQuad_with_ssub_4
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      79,	// qsub_0 -> DQuad_with_ssub_4
      79,	// qsub_1 -> DQuad_with_ssub_4
      0,	// qsub_2
      0,	// qsub_3
      79,	// ssub_0 -> DQuad_with_ssub_4
      79,	// ssub_1 -> DQuad_with_ssub_4
      79,	// ssub_2 -> DQuad_with_ssub_4
      79,	// ssub_3 -> DQuad_with_ssub_4
      79,	// ssub_4 -> DQuad_with_ssub_4
      79,	// ssub_5 -> DQuad_with_ssub_4
      80,	// ssub_6 -> DQuad_with_ssub_6
      80,	// ssub_7 -> DQuad_with_ssub_6
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      79,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_4
      79,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_4
      79,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_4
      79,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_4
      79,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_4
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_ssub_6
      80,	// dsub_0 -> DQuad_with_ssub_6
      80,	// dsub_1 -> DQuad_with_ssub_6
      80,	// dsub_2 -> DQuad_with_ssub_6
      80,	// dsub_3 -> DQuad_with_ssub_6
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      80,	// qsub_0 -> DQuad_with_ssub_6
      80,	// qsub_1 -> DQuad_with_ssub_6
      0,	// qsub_2
      0,	// qsub_3
      80,	// ssub_0 -> DQuad_with_ssub_6
      80,	// ssub_1 -> DQuad_with_ssub_6
      80,	// ssub_2 -> DQuad_with_ssub_6
      80,	// ssub_3 -> DQuad_with_ssub_6
      80,	// ssub_4 -> DQuad_with_ssub_6
      80,	// ssub_5 -> DQuad_with_ssub_6
      80,	// ssub_6 -> DQuad_with_ssub_6
      80,	// ssub_7 -> DQuad_with_ssub_6
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      80,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_6
      80,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6
      80,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_6
      80,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_6
      80,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_dsub_0_in_DPR_8
      81,	// dsub_0 -> DQuad_with_dsub_0_in_DPR_8
      81,	// dsub_1 -> DQuad_with_dsub_0_in_DPR_8
      81,	// dsub_2 -> DQuad_with_dsub_0_in_DPR_8
      81,	// dsub_3 -> DQuad_with_dsub_0_in_DPR_8
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      81,	// qsub_0 -> DQuad_with_dsub_0_in_DPR_8
      81,	// qsub_1 -> DQuad_with_dsub_0_in_DPR_8
      0,	// qsub_2
      0,	// qsub_3
      81,	// ssub_0 -> DQuad_with_dsub_0_in_DPR_8
      81,	// ssub_1 -> DQuad_with_dsub_0_in_DPR_8
      81,	// ssub_2 -> DQuad_with_dsub_0_in_DPR_8
      81,	// ssub_3 -> DQuad_with_dsub_0_in_DPR_8
      81,	// ssub_4 -> DQuad_with_dsub_0_in_DPR_8
      81,	// ssub_5 -> DQuad_with_dsub_0_in_DPR_8
      81,	// ssub_6 -> DQuad_with_dsub_0_in_DPR_8
      81,	// ssub_7 -> DQuad_with_dsub_0_in_DPR_8
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      81,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8
      81,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8
      81,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8
      81,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8
      81,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_qsub_0_in_QPR_VFP2
      82,	// dsub_0 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// dsub_1 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// dsub_2 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// dsub_3 -> DQuad_with_qsub_0_in_QPR_VFP2
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      82,	// qsub_0 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// qsub_1 -> DQuad_with_qsub_0_in_QPR_VFP2
      0,	// qsub_2
      0,	// qsub_3
      82,	// ssub_0 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// ssub_1 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// ssub_2 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// ssub_3 -> DQuad_with_qsub_0_in_QPR_VFP2
      85,	// ssub_4 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_6 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      82,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_VFP2
      82,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_VFP2
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      83,	// dsub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      83,	// dsub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      83,	// dsub_2 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      83,	// dsub_3 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      83,	// qsub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      83,	// qsub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// qsub_2
      0,	// qsub_3
      83,	// ssub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      83,	// ssub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      86,	// ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      88,	// ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      83,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      83,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      83,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      83,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      83,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_dsub_1_in_DPR_8
      84,	// dsub_0 -> DQuad_with_dsub_1_in_DPR_8
      84,	// dsub_1 -> DQuad_with_dsub_1_in_DPR_8
      84,	// dsub_2 -> DQuad_with_dsub_1_in_DPR_8
      84,	// dsub_3 -> DQuad_with_dsub_1_in_DPR_8
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      84,	// qsub_0 -> DQuad_with_dsub_1_in_DPR_8
      84,	// qsub_1 -> DQuad_with_dsub_1_in_DPR_8
      0,	// qsub_2
      0,	// qsub_3
      84,	// ssub_0 -> DQuad_with_dsub_1_in_DPR_8
      84,	// ssub_1 -> DQuad_with_dsub_1_in_DPR_8
      84,	// ssub_2 -> DQuad_with_dsub_1_in_DPR_8
      84,	// ssub_3 -> DQuad_with_dsub_1_in_DPR_8
      84,	// ssub_4 -> DQuad_with_dsub_1_in_DPR_8
      84,	// ssub_5 -> DQuad_with_dsub_1_in_DPR_8
      84,	// ssub_6 -> DQuad_with_dsub_1_in_DPR_8
      84,	// ssub_7 -> DQuad_with_dsub_1_in_DPR_8
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      84,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8
      84,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8
      84,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_1_in_DPR_8
      84,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_1_in_DPR_8
      84,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_qsub_1_in_QPR_VFP2
      85,	// dsub_0 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// dsub_1 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// dsub_2 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// dsub_3 -> DQuad_with_qsub_1_in_QPR_VFP2
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      85,	// qsub_0 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// qsub_1 -> DQuad_with_qsub_1_in_QPR_VFP2
      0,	// qsub_2
      0,	// qsub_3
      85,	// ssub_0 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_1 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_2 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_3 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_4 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_6 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      85,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_VFP2
      85,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_VFP2
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      86,	// qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      0,	// qsub_2
      0,	// qsub_3
      86,	// ssub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      88,	// ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      86,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      86,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_dsub_2_in_DPR_8
      87,	// dsub_0 -> DQuad_with_dsub_2_in_DPR_8
      87,	// dsub_1 -> DQuad_with_dsub_2_in_DPR_8
      87,	// dsub_2 -> DQuad_with_dsub_2_in_DPR_8
      87,	// dsub_3 -> DQuad_with_dsub_2_in_DPR_8
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      87,	// qsub_0 -> DQuad_with_dsub_2_in_DPR_8
      87,	// qsub_1 -> DQuad_with_dsub_2_in_DPR_8
      0,	// qsub_2
      0,	// qsub_3
      87,	// ssub_0 -> DQuad_with_dsub_2_in_DPR_8
      87,	// ssub_1 -> DQuad_with_dsub_2_in_DPR_8
      87,	// ssub_2 -> DQuad_with_dsub_2_in_DPR_8
      87,	// ssub_3 -> DQuad_with_dsub_2_in_DPR_8
      87,	// ssub_4 -> DQuad_with_dsub_2_in_DPR_8
      87,	// ssub_5 -> DQuad_with_dsub_2_in_DPR_8
      87,	// ssub_6 -> DQuad_with_dsub_2_in_DPR_8
      87,	// ssub_7 -> DQuad_with_dsub_2_in_DPR_8
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      87,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8
      87,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8
      87,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_2_in_DPR_8
      87,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_2_in_DPR_8
      87,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// dsub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// dsub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// dsub_2 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// dsub_3 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      88,	// qsub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// qsub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// qsub_2
      0,	// qsub_3
      88,	// ssub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_2 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_3 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_4 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      88,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      88,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_dsub_3_in_DPR_8
      89,	// dsub_0 -> DQuad_with_dsub_3_in_DPR_8
      89,	// dsub_1 -> DQuad_with_dsub_3_in_DPR_8
      89,	// dsub_2 -> DQuad_with_dsub_3_in_DPR_8
      89,	// dsub_3 -> DQuad_with_dsub_3_in_DPR_8
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      89,	// qsub_0 -> DQuad_with_dsub_3_in_DPR_8
      89,	// qsub_1 -> DQuad_with_dsub_3_in_DPR_8
      0,	// qsub_2
      0,	// qsub_3
      89,	// ssub_0 -> DQuad_with_dsub_3_in_DPR_8
      89,	// ssub_1 -> DQuad_with_dsub_3_in_DPR_8
      89,	// ssub_2 -> DQuad_with_dsub_3_in_DPR_8
      89,	// ssub_3 -> DQuad_with_dsub_3_in_DPR_8
      89,	// ssub_4 -> DQuad_with_dsub_3_in_DPR_8
      89,	// ssub_5 -> DQuad_with_dsub_3_in_DPR_8
      89,	// ssub_6 -> DQuad_with_dsub_3_in_DPR_8
      89,	// ssub_7 -> DQuad_with_dsub_3_in_DPR_8
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      89,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8
      89,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8
      89,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8
      89,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8
      89,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// dsub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// dsub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// dsub_2 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// dsub_3 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      90,	// qsub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// qsub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// qsub_2
      0,	// qsub_3
      90,	// ssub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// ssub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// ssub_2 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// ssub_3 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// ssub_4 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// ssub_6 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      90,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      90,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_qsub_0_in_QPR_8
      91,	// dsub_0 -> DQuad_with_qsub_0_in_QPR_8
      91,	// dsub_1 -> DQuad_with_qsub_0_in_QPR_8
      91,	// dsub_2 -> DQuad_with_qsub_0_in_QPR_8
      91,	// dsub_3 -> DQuad_with_qsub_0_in_QPR_8
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      91,	// qsub_0 -> DQuad_with_qsub_0_in_QPR_8
      91,	// qsub_1 -> DQuad_with_qsub_0_in_QPR_8
      0,	// qsub_2
      0,	// qsub_3
      91,	// ssub_0 -> DQuad_with_qsub_0_in_QPR_8
      91,	// ssub_1 -> DQuad_with_qsub_0_in_QPR_8
      91,	// ssub_2 -> DQuad_with_qsub_0_in_QPR_8
      91,	// ssub_3 -> DQuad_with_qsub_0_in_QPR_8
      91,	// ssub_4 -> DQuad_with_qsub_0_in_QPR_8
      91,	// ssub_5 -> DQuad_with_qsub_0_in_QPR_8
      91,	// ssub_6 -> DQuad_with_qsub_0_in_QPR_8
      91,	// ssub_7 -> DQuad_with_qsub_0_in_QPR_8
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      91,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8
      91,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8
      91,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_8
      91,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_8
      91,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_qsub_1_in_QPR_8
      92,	// dsub_0 -> DQuad_with_qsub_1_in_QPR_8
      92,	// dsub_1 -> DQuad_with_qsub_1_in_QPR_8
      92,	// dsub_2 -> DQuad_with_qsub_1_in_QPR_8
      92,	// dsub_3 -> DQuad_with_qsub_1_in_QPR_8
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      92,	// qsub_0 -> DQuad_with_qsub_1_in_QPR_8
      92,	// qsub_1 -> DQuad_with_qsub_1_in_QPR_8
      0,	// qsub_2
      0,	// qsub_3
      92,	// ssub_0 -> DQuad_with_qsub_1_in_QPR_8
      92,	// ssub_1 -> DQuad_with_qsub_1_in_QPR_8
      92,	// ssub_2 -> DQuad_with_qsub_1_in_QPR_8
      92,	// ssub_3 -> DQuad_with_qsub_1_in_QPR_8
      92,	// ssub_4 -> DQuad_with_qsub_1_in_QPR_8
      92,	// ssub_5 -> DQuad_with_qsub_1_in_QPR_8
      92,	// ssub_6 -> DQuad_with_qsub_1_in_QPR_8
      92,	// ssub_7 -> DQuad_with_qsub_1_in_QPR_8
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      92,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8
      92,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8
      92,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_8
      92,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_8
      92,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      93,	// qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      0,	// qsub_2
      0,	// qsub_3
      93,	// ssub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// ssub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// ssub_6 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      93,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      93,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// dsub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// dsub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// dsub_2 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// dsub_3 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// dsub_4
      0,	// dsub_5
      0,	// dsub_6
      0,	// dsub_7
      0,	// gsub_0
      0,	// gsub_1
      0,	// qqsub_0
      0,	// qqsub_1
      94,	// qsub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// qsub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// qsub_2
      0,	// qsub_3
      94,	// ssub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// ssub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// ssub_2 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// ssub_3 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// ssub_4 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// ssub_6 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_8
      0,	// ssub_9
      0,	// ssub_10
      0,	// ssub_11
      0,	// ssub_12
      0,	// ssub_13
      0,	// dsub_7_then_ssub_0
      0,	// dsub_7_then_ssub_1
      94,	// ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      94,	// ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5
      0,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_6_ssub_7_dsub_5
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5
      0,	// ssub_6_ssub_7_dsub_5_dsub_7
      0,	// ssub_6_ssub_7_ssub_8_ssub_9
      0,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_ssub_12_ssub_13
      0,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13
      0,	// dsub_5_dsub_7
      0,	// dsub_5_ssub_12_ssub_13_dsub_7
      0,	// dsub_5_ssub_12_ssub_13
      0,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2
    },
    {	// QQQQPR
      95,	// dsub_0 -> QQQQPR
      95,	// dsub_1 -> QQQQPR
      95,	// dsub_2 -> QQQQPR
      95,	// dsub_3 -> QQQQPR
      95,	// dsub_4 -> QQQQPR
      95,	// dsub_5 -> QQQQPR
      95,	// dsub_6 -> QQQQPR
      95,	// dsub_7 -> QQQQPR
      0,	// gsub_0
      0,	// gsub_1
      95,	// qqsub_0 -> QQQQPR
      95,	// qqsub_1 -> QQQQPR
      95,	// qsub_0 -> QQQQPR
      95,	// qsub_1 -> QQQQPR
      95,	// qsub_2 -> QQQQPR
      95,	// qsub_3 -> QQQQPR
      96,	// ssub_0 -> QQQQPR_with_ssub_0
      96,	// ssub_1 -> QQQQPR_with_ssub_0
      96,	// ssub_2 -> QQQQPR_with_ssub_0
      96,	// ssub_3 -> QQQQPR_with_ssub_0
      97,	// ssub_4 -> QQQQPR_with_ssub_4
      97,	// ssub_5 -> QQQQPR_with_ssub_4
      97,	// ssub_6 -> QQQQPR_with_ssub_4
      97,	// ssub_7 -> QQQQPR_with_ssub_4
      98,	// ssub_8 -> QQQQPR_with_ssub_8
      98,	// ssub_9 -> QQQQPR_with_ssub_8
      98,	// ssub_10 -> QQQQPR_with_ssub_8
      98,	// ssub_11 -> QQQQPR_with_ssub_8
      99,	// ssub_12 -> QQQQPR_with_ssub_12
      99,	// ssub_13 -> QQQQPR_with_ssub_12
      99,	// dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
      99,	// dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
      95,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR
      95,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR
      95,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR
      95,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR
      95,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR
      95,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR
      95,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR
      95,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR
      95,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR
      95,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR
      95,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR
      95,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR
      95,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR
      95,	// ssub_6_ssub_7_dsub_5 -> QQQQPR
      95,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR
      95,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR
      95,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR
      95,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR
      95,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR
      95,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR
      95,	// dsub_5_dsub_7 -> QQQQPR
      95,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR
      95,	// dsub_5_ssub_12_ssub_13 -> QQQQPR
      95,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR
    },
    {	// QQQQPR_with_ssub_0
      96,	// dsub_0 -> QQQQPR_with_ssub_0
      96,	// dsub_1 -> QQQQPR_with_ssub_0
      96,	// dsub_2 -> QQQQPR_with_ssub_0
      96,	// dsub_3 -> QQQQPR_with_ssub_0
      96,	// dsub_4 -> QQQQPR_with_ssub_0
      96,	// dsub_5 -> QQQQPR_with_ssub_0
      96,	// dsub_6 -> QQQQPR_with_ssub_0
      96,	// dsub_7 -> QQQQPR_with_ssub_0
      0,	// gsub_0
      0,	// gsub_1
      96,	// qqsub_0 -> QQQQPR_with_ssub_0
      96,	// qqsub_1 -> QQQQPR_with_ssub_0
      96,	// qsub_0 -> QQQQPR_with_ssub_0
      96,	// qsub_1 -> QQQQPR_with_ssub_0
      96,	// qsub_2 -> QQQQPR_with_ssub_0
      96,	// qsub_3 -> QQQQPR_with_ssub_0
      96,	// ssub_0 -> QQQQPR_with_ssub_0
      96,	// ssub_1 -> QQQQPR_with_ssub_0
      96,	// ssub_2 -> QQQQPR_with_ssub_0
      96,	// ssub_3 -> QQQQPR_with_ssub_0
      97,	// ssub_4 -> QQQQPR_with_ssub_4
      97,	// ssub_5 -> QQQQPR_with_ssub_4
      97,	// ssub_6 -> QQQQPR_with_ssub_4
      97,	// ssub_7 -> QQQQPR_with_ssub_4
      98,	// ssub_8 -> QQQQPR_with_ssub_8
      98,	// ssub_9 -> QQQQPR_with_ssub_8
      98,	// ssub_10 -> QQQQPR_with_ssub_8
      98,	// ssub_11 -> QQQQPR_with_ssub_8
      99,	// ssub_12 -> QQQQPR_with_ssub_12
      99,	// ssub_13 -> QQQQPR_with_ssub_12
      99,	// dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
      99,	// dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
      96,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_0
      96,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_0
      96,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_0
      96,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_0
      96,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_0
      96,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
      96,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
      96,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_0
      96,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_0
      96,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
      96,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
      96,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
      96,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
      96,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_0
      96,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_0
      96,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_0
      96,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0
      96,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
      96,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
      96,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
      96,	// dsub_5_dsub_7 -> QQQQPR_with_ssub_0
      96,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_0
      96,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0
      96,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_0
    },
    {	// QQQQPR_with_ssub_4
      97,	// dsub_0 -> QQQQPR_with_ssub_4
      97,	// dsub_1 -> QQQQPR_with_ssub_4
      97,	// dsub_2 -> QQQQPR_with_ssub_4
      97,	// dsub_3 -> QQQQPR_with_ssub_4
      97,	// dsub_4 -> QQQQPR_with_ssub_4
      97,	// dsub_5 -> QQQQPR_with_ssub_4
      97,	// dsub_6 -> QQQQPR_with_ssub_4
      97,	// dsub_7 -> QQQQPR_with_ssub_4
      0,	// gsub_0
      0,	// gsub_1
      97,	// qqsub_0 -> QQQQPR_with_ssub_4
      97,	// qqsub_1 -> QQQQPR_with_ssub_4
      97,	// qsub_0 -> QQQQPR_with_ssub_4
      97,	// qsub_1 -> QQQQPR_with_ssub_4
      97,	// qsub_2 -> QQQQPR_with_ssub_4
      97,	// qsub_3 -> QQQQPR_with_ssub_4
      97,	// ssub_0 -> QQQQPR_with_ssub_4
      97,	// ssub_1 -> QQQQPR_with_ssub_4
      97,	// ssub_2 -> QQQQPR_with_ssub_4
      97,	// ssub_3 -> QQQQPR_with_ssub_4
      97,	// ssub_4 -> QQQQPR_with_ssub_4
      97,	// ssub_5 -> QQQQPR_with_ssub_4
      97,	// ssub_6 -> QQQQPR_with_ssub_4
      97,	// ssub_7 -> QQQQPR_with_ssub_4
      98,	// ssub_8 -> QQQQPR_with_ssub_8
      98,	// ssub_9 -> QQQQPR_with_ssub_8
      98,	// ssub_10 -> QQQQPR_with_ssub_8
      98,	// ssub_11 -> QQQQPR_with_ssub_8
      99,	// ssub_12 -> QQQQPR_with_ssub_12
      99,	// ssub_13 -> QQQQPR_with_ssub_12
      99,	// dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
      99,	// dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
      97,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_4
      97,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_4
      97,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_4
      97,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_4
      97,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_4
      97,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
      97,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
      97,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_4
      97,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_4
      97,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
      97,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
      97,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
      97,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
      97,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_4
      97,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_4
      97,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_4
      97,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4
      97,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
      97,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
      97,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
      97,	// dsub_5_dsub_7 -> QQQQPR_with_ssub_4
      97,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_4
      97,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4
      97,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_4
    },
    {	// QQQQPR_with_ssub_8
      98,	// dsub_0 -> QQQQPR_with_ssub_8
      98,	// dsub_1 -> QQQQPR_with_ssub_8
      98,	// dsub_2 -> QQQQPR_with_ssub_8
      98,	// dsub_3 -> QQQQPR_with_ssub_8
      98,	// dsub_4 -> QQQQPR_with_ssub_8
      98,	// dsub_5 -> QQQQPR_with_ssub_8
      98,	// dsub_6 -> QQQQPR_with_ssub_8
      98,	// dsub_7 -> QQQQPR_with_ssub_8
      0,	// gsub_0
      0,	// gsub_1
      98,	// qqsub_0 -> QQQQPR_with_ssub_8
      98,	// qqsub_1 -> QQQQPR_with_ssub_8
      98,	// qsub_0 -> QQQQPR_with_ssub_8
      98,	// qsub_1 -> QQQQPR_with_ssub_8
      98,	// qsub_2 -> QQQQPR_with_ssub_8
      98,	// qsub_3 -> QQQQPR_with_ssub_8
      98,	// ssub_0 -> QQQQPR_with_ssub_8
      98,	// ssub_1 -> QQQQPR_with_ssub_8
      98,	// ssub_2 -> QQQQPR_with_ssub_8
      98,	// ssub_3 -> QQQQPR_with_ssub_8
      98,	// ssub_4 -> QQQQPR_with_ssub_8
      98,	// ssub_5 -> QQQQPR_with_ssub_8
      98,	// ssub_6 -> QQQQPR_with_ssub_8
      98,	// ssub_7 -> QQQQPR_with_ssub_8
      98,	// ssub_8 -> QQQQPR_with_ssub_8
      98,	// ssub_9 -> QQQQPR_with_ssub_8
      98,	// ssub_10 -> QQQQPR_with_ssub_8
      98,	// ssub_11 -> QQQQPR_with_ssub_8
      99,	// ssub_12 -> QQQQPR_with_ssub_12
      99,	// ssub_13 -> QQQQPR_with_ssub_12
      99,	// dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
      99,	// dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
      98,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_8
      98,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_8
      98,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_8
      98,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_8
      98,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_8
      98,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
      98,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
      98,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_8
      98,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_8
      98,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
      98,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
      98,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
      98,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
      98,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_8
      98,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_8
      98,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_8
      98,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8
      98,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
      98,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
      98,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
      98,	// dsub_5_dsub_7 -> QQQQPR_with_ssub_8
      98,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_8
      98,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8
      98,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_8
    },
    {	// QQQQPR_with_ssub_12
      99,	// dsub_0 -> QQQQPR_with_ssub_12
      99,	// dsub_1 -> QQQQPR_with_ssub_12
      99,	// dsub_2 -> QQQQPR_with_ssub_12
      99,	// dsub_3 -> QQQQPR_with_ssub_12
      99,	// dsub_4 -> QQQQPR_with_ssub_12
      99,	// dsub_5 -> QQQQPR_with_ssub_12
      99,	// dsub_6 -> QQQQPR_with_ssub_12
      99,	// dsub_7 -> QQQQPR_with_ssub_12
      0,	// gsub_0
      0,	// gsub_1
      99,	// qqsub_0 -> QQQQPR_with_ssub_12
      99,	// qqsub_1 -> QQQQPR_with_ssub_12
      99,	// qsub_0 -> QQQQPR_with_ssub_12
      99,	// qsub_1 -> QQQQPR_with_ssub_12
      99,	// qsub_2 -> QQQQPR_with_ssub_12
      99,	// qsub_3 -> QQQQPR_with_ssub_12
      99,	// ssub_0 -> QQQQPR_with_ssub_12
      99,	// ssub_1 -> QQQQPR_with_ssub_12
      99,	// ssub_2 -> QQQQPR_with_ssub_12
      99,	// ssub_3 -> QQQQPR_with_ssub_12
      99,	// ssub_4 -> QQQQPR_with_ssub_12
      99,	// ssub_5 -> QQQQPR_with_ssub_12
      99,	// ssub_6 -> QQQQPR_with_ssub_12
      99,	// ssub_7 -> QQQQPR_with_ssub_12
      99,	// ssub_8 -> QQQQPR_with_ssub_12
      99,	// ssub_9 -> QQQQPR_with_ssub_12
      99,	// ssub_10 -> QQQQPR_with_ssub_12
      99,	// ssub_11 -> QQQQPR_with_ssub_12
      99,	// ssub_12 -> QQQQPR_with_ssub_12
      99,	// ssub_13 -> QQQQPR_with_ssub_12
      99,	// dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12
      99,	// dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12
      99,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_12
      99,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_12
      99,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_12
      99,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_12
      99,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_12
      99,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
      99,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
      99,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_12
      99,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_12
      99,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
      99,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
      99,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
      99,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
      99,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_12
      99,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_12
      99,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_12
      99,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12
      99,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
      99,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
      99,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
      99,	// dsub_5_dsub_7 -> QQQQPR_with_ssub_12
      99,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_12
      99,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12
      99,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_12
    },
    {	// QQQQPR_with_dsub_0_in_DPR_8
      100,	// dsub_0 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// dsub_1 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// dsub_2 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// dsub_3 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// dsub_4 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// dsub_6 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
      0,	// gsub_0
      0,	// gsub_1
      100,	// qqsub_0 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// qqsub_1 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// qsub_0 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// qsub_1 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// qsub_2 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// qsub_3 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_0 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_1 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_2 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_3 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_4 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_6 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_8 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_10 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_11 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_12 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// dsub_7_then_ssub_0 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// dsub_7_then_ssub_1 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8
      100,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_0_in_DPR_8
    },
    {	// QQQQPR_with_dsub_2_in_DPR_8
      101,	// dsub_0 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// dsub_1 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// dsub_2 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// dsub_3 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// dsub_4 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// dsub_6 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
      0,	// gsub_0
      0,	// gsub_1
      101,	// qqsub_0 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// qqsub_1 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// qsub_0 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// qsub_1 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// qsub_2 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// qsub_3 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_0 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_1 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_2 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_3 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_4 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_6 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_8 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_10 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_11 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_12 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// dsub_7_then_ssub_0 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// dsub_7_then_ssub_1 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8
      101,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_2_in_DPR_8
    },
    {	// QQQQPR_with_dsub_4_in_DPR_8
      102,	// dsub_0 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// dsub_1 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// dsub_2 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// dsub_3 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// dsub_4 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// dsub_6 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
      0,	// gsub_0
      0,	// gsub_1
      102,	// qqsub_0 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// qqsub_1 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// qsub_0 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// qsub_1 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// qsub_2 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// qsub_3 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_0 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_1 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_2 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_3 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_4 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_6 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_8 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_10 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_11 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_12 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// dsub_7_then_ssub_0 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// dsub_7_then_ssub_1 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8
      102,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_4_in_DPR_8
    },
    {	// QQQQPR_with_dsub_6_in_DPR_8
      103,	// dsub_0 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// dsub_1 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// dsub_2 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// dsub_3 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// dsub_4 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// dsub_6 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
      0,	// gsub_0
      0,	// gsub_1
      103,	// qqsub_0 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// qqsub_1 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// qsub_0 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// qsub_1 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// qsub_2 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// qsub_3 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_0 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_1 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_2 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_3 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_4 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_6 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_8 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_10 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_11 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_12 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// dsub_7_then_ssub_0 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// dsub_7_then_ssub_1 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8
      103,	// ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_6_in_DPR_8
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 56 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

/// Get the weight in units of pressure for this register class.
const RegClassWeight &ARMGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {1, 32},  	// HPR
    {1, 32},  	// SPR
    {1, 16},  	// GPR
    {1, 16},  	// GPRwithAPSR
    {1, 16},  	// SPR_8
    {1, 15},  	// GPRnopc
    {1, 14},  	// rGPR
    {1, 9},  	// tGPRwithpc
    {1, 8},  	// hGPR
    {1, 8},  	// tGPR
    {1, 7},  	// GPRnopc_and_hGPR
    {1, 6},  	// hGPR_and_rGPR
    {1, 5},  	// tcGPR
    {1, 4},  	// tGPR_and_tcGPR
    {0, 0},  	// CCR
    {1, 1},  	// GPRsp
    {1, 1},  	// hGPR_and_tGPRwithpc
    {1, 1},  	// hGPR_and_tcGPR
    {2, 64},  	// DPR
    {2, 32},  	// DPR_VFP2
    {2, 16},  	// DPR_8
    {2, 14},  	// GPRPair
    {2, 12},  	// GPRPair_with_gsub_1_in_rGPR
    {2, 8},  	// GPRPair_with_gsub_0_in_tGPR
    {2, 6},  	// GPRPair_with_gsub_0_in_hGPR
    {2, 6},  	// GPRPair_with_gsub_0_in_tcGPR
    {2, 4},  	// GPRPair_with_gsub_1_in_hGPR_and_rGPR
    {2, 4},  	// GPRPair_with_gsub_1_in_tcGPR
    {2, 2},  	// GPRPair_with_gsub_1_in_GPRsp
    {4, 64},  	// DPairSpc
    {4, 36},  	// DPairSpc_with_ssub_0
    {4, 32},  	// DPairSpc_with_ssub_4
    {4, 20},  	// DPairSpc_with_dsub_0_in_DPR_8
    {4, 16},  	// DPairSpc_with_dsub_2_in_DPR_8
    {4, 64},  	// DPair
    {4, 34},  	// DPair_with_ssub_0
    {4, 64},  	// QPR
    {4, 32},  	// DPair_with_ssub_2
    {4, 18},  	// DPair_with_dsub_0_in_DPR_8
    {4, 32},  	// QPR_VFP2
    {4, 16},  	// DPair_with_dsub_1_in_DPR_8
    {4, 16},  	// QPR_8
    {6, 64},  	// DTriple
    {6, 64},  	// DTripleSpc
    {6, 40},  	// DTripleSpc_with_ssub_0
    {6, 36},  	// DTriple_with_ssub_0
    {6, 62},  	// DTriple_with_qsub_0_in_QPR
    {6, 34},  	// DTriple_with_ssub_2
    {6, 62},  	// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
    {6, 36},  	// DTripleSpc_with_ssub_4
    {6, 32},  	// DTriple_with_ssub_4
    {6, 32},  	// DTripleSpc_with_ssub_8
    {6, 24},  	// DTripleSpc_with_dsub_0_in_DPR_8
    {6, 20},  	// DTriple_with_dsub_0_in_DPR_8
    {6, 34},  	// DTriple_with_qsub_0_in_QPR_VFP2
    {6, 34},  	// DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
    {6, 18},  	// DTriple_with_dsub_1_in_DPR_8
    {6, 30},  	// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
    {6, 30},  	// DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR
    {6, 20},  	// DTripleSpc_with_dsub_2_in_DPR_8
    {6, 16},  	// DTriple_with_dsub_2_in_DPR_8
    {6, 16},  	// DTripleSpc_with_dsub_4_in_DPR_8
    {6, 18},  	// DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
    {6, 18},  	// DTriple_with_qsub_0_in_QPR_8
    {6, 14},  	// DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR
    {6, 14},  	// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
    {6, 64},  	// DQuadSpc
    {6, 40},  	// DQuadSpc_with_ssub_0
    {6, 36},  	// DQuadSpc_with_ssub_4
    {6, 32},  	// DQuadSpc_with_ssub_8
    {6, 24},  	// DQuadSpc_with_dsub_0_in_DPR_8
    {6, 20},  	// DQuadSpc_with_dsub_2_in_DPR_8
    {6, 16},  	// DQuadSpc_with_dsub_4_in_DPR_8
    {8, 64},  	// DQuad
    {8, 38},  	// DQuad_with_ssub_0
    {8, 36},  	// DQuad_with_ssub_2
    {8, 64},  	// QQPR
    {8, 60},  	// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
    {8, 34},  	// DQuad_with_ssub_4
    {8, 32},  	// DQuad_with_ssub_6
    {8, 22},  	// DQuad_with_dsub_0_in_DPR_8
    {8, 36},  	// DQuad_with_qsub_0_in_QPR_VFP2
    {8, 36},  	// DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
    {8, 20},  	// DQuad_with_dsub_1_in_DPR_8
    {8, 32},  	// DQuad_with_qsub_1_in_QPR_VFP2
    {8, 32},  	// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
    {8, 18},  	// DQuad_with_dsub_2_in_DPR_8
    {8, 28},  	// DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
    {8, 16},  	// DQuad_with_dsub_3_in_DPR_8
    {8, 20},  	// DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
    {8, 20},  	// DQuad_with_qsub_0_in_QPR_8
    {8, 16},  	// DQuad_with_qsub_1_in_QPR_8
    {8, 16},  	// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8
    {8, 12},  	// DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
    {16, 64},  	// QQQQPR
    {16, 44},  	// QQQQPR_with_ssub_0
    {16, 40},  	// QQQQPR_with_ssub_4
    {16, 36},  	// QQQQPR_with_ssub_8
    {16, 32},  	// QQQQPR_with_ssub_12
    {16, 28},  	// QQQQPR_with_dsub_0_in_DPR_8
    {16, 24},  	// QQQQPR_with_dsub_2_in_DPR_8
    {16, 20},  	// QQQQPR_with_dsub_4_in_DPR_8
    {16, 16},  	// QQQQPR_with_dsub_6_in_DPR_8
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned ARMGenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
  assert(RegUnit < 77 && "invalid register unit");
  static const uint8_t RUWeightTable[] = {
    0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
  return RUWeightTable[RegUnit];
}


// Get the number of dimensions of register pressure.
unsigned ARMGenRegisterInfo::getNumRegPressureSets() const {
  return 21;
}

// Get the name of this register unit pressure set.
const char *ARMGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *const PressureNameTable[] = {
    "hGPR_and_tGPRwithpc",
    "GPRsp",
    "tcGPR",
    "hGPR",
    "tGPR",
    "hGPR+tcGPR",
    "GPR",
    "DQuad_with_dsub_0_in_DPR_8",
    "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2",
    "HPR",
    "DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR",
    "DPair_with_ssub_0",
    "DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR",
    "DPairSpc_with_ssub_0",
    "DQuad_with_ssub_0",
    "DTripleSpc_with_ssub_0",
    "QQQQPR_with_ssub_0",
    "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR",
    "DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR",
    "DTriple_with_qsub_0_in_QPR",
    "DPR",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned ARMGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    1,  	// 0: hGPR_and_tGPRwithpc
    2,  	// 1: GPRsp
    6,  	// 2: tcGPR
    8,  	// 3: hGPR
    11,  	// 4: tGPR
    12,  	// 5: hGPR+tcGPR
    17,  	// 6: GPR
    24,  	// 7: DQuad_with_dsub_0_in_DPR_8
    32,  	// 8: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2
    32,  	// 9: HPR
    34,  	// 10: DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
    34,  	// 11: DPair_with_ssub_0
    36,  	// 12: DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
    36,  	// 13: DPairSpc_with_ssub_0
    38,  	// 14: DQuad_with_ssub_0
    40,  	// 15: DTripleSpc_with_ssub_0
    44,  	// 16: QQQQPR_with_ssub_0
    60,  	// 17: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
    62,  	// 18: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR
    62,  	// 19: DTriple_with_qsub_0_in_QPR
    64,  	// 20: DPR
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 4, 6, -1,
  /* 3 */ 3, 5, 6, -1,
  /* 7 */ 2, 4, 5, 6, -1,
  /* 12 */ 0, 3, 4, 5, 6, -1,
  /* 18 */ 1, 2, 3, 4, 5, 6, -1,
  /* 25 */ 18, 20, -1,
  /* 28 */ 7, 9, 11, 13, 14, 15, 16, 19, 20, -1,
  /* 38 */ 12, 14, 15, 16, 17, 18, 19, 20, -1,
  /* 47 */ 10, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1,
  /* 58 */ 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1,
  /* 71 */ 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int* ARMGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
    29,29,1,1,28,1,1,0,3,0,3,3,7,7,2,18,12,18,26,29,28,1,1,0,3,7,3,7,18,26,31,29,28,28,26,30,26,29,28,29,28,28,26,26,33,31,35,30,25,31,29,29,28,28,30,47,28,72,29,28,28,28,71,28,28,71,26,33,31,29,28,28,28,26,32,31,26,42,30,29,28,31,38,28,29,58,28,72,28,71,28,28,71,71,26,34,33,31,29,29,28,28,28,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int* ARMGenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
  assert(RegUnit < 77 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
    2,1,2,2,2,2,2,2,3,12,18,2,28,28,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,71,72,72,72,72,72,72,72,72,58,47,38,40,41,41,42,42,42,42,42,42,42,42,42,25,2,2,2,2,7,7,7,7,0,0,0,0,3,3,3,3,18,};
  return &RCSetsTable[RUSetStartTable[RegUnit]];
}

extern const MCRegisterDesc ARMRegDesc[];
extern const MCPhysReg ARMRegDiffLists[];
extern const LaneBitmask ARMLaneMaskLists[];
extern const char ARMRegStrings[];
extern const char ARMRegClassStrings[];
extern const MCPhysReg ARMRegUnitRoots[][2];
extern const uint16_t ARMSubRegIdxLists[];
extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[];
extern const uint16_t ARMRegEncodingTable[];
// ARM Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[];
extern const unsigned ARMDwarfFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[];
extern const unsigned ARMEHFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[];
extern const unsigned ARMDwarfFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[];
extern const unsigned ARMEHFlavour0L2DwarfSize;

ARMGenRegisterInfo::
ARMGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(ARMRegInfoDesc, RegisterClasses, RegisterClasses+103,
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFFF), RegClassInfos, HwMode) {
  InitMCRegisterInfo(ARMRegDesc, 289, RA, PC,
                     ARMMCRegisterClasses, 103,
                     ARMRegUnitRoots,
                     77,
                     ARMRegDiffLists,
                     ARMLaneMaskLists,
                     ARMRegStrings,
                     ARMRegClassStrings,
                     ARMSubRegIdxLists,
                     57,
                     ARMSubRegIdxRanges,
                     ARMRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true);
    break;
  }
}

static const MCPhysReg CSR_AAPCS_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
static const uint32_t CSR_AAPCS_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003fc0, 0x1f807fff, 0x000e0000, 0x3f00f001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
static const MCPhysReg CSR_AAPCS_SplitPush_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
static const uint32_t CSR_AAPCS_SplitPush_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003fc0, 0x1f807fff, 0x000e0000, 0x3f00f001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
static const MCPhysReg CSR_AAPCS_SplitPush_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
static const uint32_t CSR_AAPCS_SplitPush_SwiftError_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003bc0, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
static const MCPhysReg CSR_AAPCS_SwiftError_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
static const uint32_t CSR_AAPCS_SwiftError_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003bc0, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
static const MCPhysReg CSR_AAPCS_ThisReturn_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
static const uint32_t CSR_AAPCS_ThisReturn_RegMask[] = { 0x3fc00400, 0x03c00000, 0x80003fc4, 0x1f807fff, 0x000e0000, 0x3f00f001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
static const MCPhysReg CSR_FIQ_SaveList[] = { ARM::LR, ARM::R11, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
static const uint32_t CSR_FIQ_RegMask[] = { 0x00000400, 0x00000000, 0x000023fc, 0x00000000, 0x00000000, 0x00003c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_FPRegs_SaveList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 0 };
static const uint32_t CSR_FPRegs_RegMask[] = { 0xffffc000, 0xfffc3fff, 0xffff8003, 0xffffffff, 0xffffffff, 0xffff01ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000001, };
static const MCPhysReg CSR_GenericInt_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
static const uint32_t CSR_GenericInt_RegMask[] = { 0x00000400, 0x00000000, 0x00007ffc, 0x00000000, 0x00000000, 0x0000fc00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_iOS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
static const uint32_t CSR_iOS_RegMask[] = { 0x3fc00400, 0x03c00000, 0x800037c0, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
static const MCPhysReg CSR_iOS_CXX_TLS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R12, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
static const uint32_t CSR_iOS_CXX_TLS_RegMask[] = { 0xffffc400, 0xfffc3fff, 0xfffffffb, 0xffffffff, 0xffffffff, 0xfffff9ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000001, };
static const MCPhysReg CSR_iOS_CXX_TLS_PE_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R7, ARM::R5, ARM::R4, 0 };
static const uint32_t CSR_iOS_CXX_TLS_PE_RegMask[] = { 0x00000400, 0x00000000, 0x000062c0, 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_iOS_CXX_TLS_ViaCopy_SaveList[] = { ARM::R6, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
static const uint32_t CSR_iOS_CXX_TLS_ViaCopy_RegMask[] = { 0xffffc000, 0xfffc3fff, 0xffff9d3b, 0xffffffff, 0xffffffff, 0xffff49ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000001, };
static const MCPhysReg CSR_iOS_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
static const uint32_t CSR_iOS_SwiftError_RegMask[] = { 0x3fc00400, 0x03c00000, 0x800033c0, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };
static const MCPhysReg CSR_iOS_TLSCall_SaveList[] = { ARM::LR, ARM::SP, ARM::R11, ARM::R10, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
static const uint32_t CSR_iOS_TLSCall_RegMask[] = { 0xffffd400, 0xfffc3fff, 0xffffb7fb, 0xffffffff, 0xffffffff, 0xffffb9ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000001, };
static const MCPhysReg CSR_iOS_ThisReturn_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
static const uint32_t CSR_iOS_ThisReturn_RegMask[] = { 0x3fc00400, 0x03c00000, 0x800037c4, 0x1f807fff, 0x000e0000, 0x3f00b001, 0x03c00000, 0x000c0000, 0x01800700, 0x00000000, };


ArrayRef<const uint32_t *> ARMGenRegisterInfo::getRegMasks() const {
  static const uint32_t *const Masks[] = {
    CSR_AAPCS_RegMask,
    CSR_AAPCS_SplitPush_RegMask,
    CSR_AAPCS_SplitPush_SwiftError_RegMask,
    CSR_AAPCS_SwiftError_RegMask,
    CSR_AAPCS_ThisReturn_RegMask,
    CSR_FIQ_RegMask,
    CSR_FPRegs_RegMask,
    CSR_GenericInt_RegMask,
    CSR_NoRegs_RegMask,
    CSR_iOS_RegMask,
    CSR_iOS_CXX_TLS_RegMask,
    CSR_iOS_CXX_TLS_PE_RegMask,
    CSR_iOS_CXX_TLS_ViaCopy_RegMask,
    CSR_iOS_SwiftError_RegMask,
    CSR_iOS_TLSCall_RegMask,
    CSR_iOS_ThisReturn_RegMask,
  };
  return makeArrayRef(Masks);
}

ArrayRef<const char *> ARMGenRegisterInfo::getRegMaskNames() const {
  static const char *const Names[] = {
    "CSR_AAPCS",
    "CSR_AAPCS_SplitPush",
    "CSR_AAPCS_SplitPush_SwiftError",
    "CSR_AAPCS_SwiftError",
    "CSR_AAPCS_ThisReturn",
    "CSR_FIQ",
    "CSR_FPRegs",
    "CSR_GenericInt",
    "CSR_NoRegs",
    "CSR_iOS",
    "CSR_iOS_CXX_TLS",
    "CSR_iOS_CXX_TLS_PE",
    "CSR_iOS_CXX_TLS_ViaCopy",
    "CSR_iOS_SwiftError",
    "CSR_iOS_TLSCall",
    "CSR_iOS_ThisReturn",
  };
  return makeArrayRef(Names);
}

const ARMFrameLowering *
ARMGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const ARMFrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

#endif // GET_REGINFO_TARGET_DESC

